MC9S08DZ128CLF Freescale Semiconductor, MC9S08DZ128CLF Datasheet - Page 401
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MC9S08DZ128CLF
Manufacturer Part Number
MC9S08DZ128CLF
Description
MCU 8BIT 128K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.MC9S08DV96CLF.pdf
(458 pages)
2.MC9S08DV96CLF.pdf
(4 pages)
3.MC9S08DZ128CLF.pdf
(4 pages)
4.MC9S08DZ96MLL.pdf
(4 pages)
Specifications of MC9S08DZ128CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Package
48LQFP
Family Name
HCS08
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
87
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
24-chx12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ128CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC9S08DV96CLF PDF datasheet
- MC9S08DV96CLF PDF datasheet #2
- MC9S08DZ128CLF PDF datasheet #3
- MC9S08DZ96MLL PDF datasheet #4
- Current page: 401 of 458
- Download datasheet (5Mb)
18.3.3.8
1
Freescale Semiconductor
end-run
Module Base + 0x0007
end-run
Bits 15–8
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Bits 7–0
Reset
Field
Field
POR
W
R
1
FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register
is not used in event only modes and will read a $00 for valid FIFO words.
Bit 7
FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.
Debug FIFO Low Register (DBGFL)
U
0
7
= Unimplemented or Reserved
Bit 6
U
0
6
Figure 18-9. Debug FIFO Low Register (DBGFL)
Table 18-10. DBGFL Field Descriptions
Table 18-9. DBGFH Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
Bit 5
U
0
5
Bit 4
U
0
4
Description
Description
Bit 3
U
0
3
Chapter 18 Debug Module (S08DBGV3) (128K)
Bit 2
U
0
2
Bit 1
U
0
1
Bit 0
U
0
0
401
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