MC9S08DZ128CLF Freescale Semiconductor, MC9S08DZ128CLF Datasheet - Page 315
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MC9S08DZ128CLF
Manufacturer Part Number
MC9S08DZ128CLF
Description
MCU 8BIT 128K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.MC9S08DV96CLF.pdf
(458 pages)
2.MC9S08DV96CLF.pdf
(4 pages)
3.MC9S08DZ128CLF.pdf
(4 pages)
4.MC9S08DZ96MLL.pdf
(4 pages)
Specifications of MC9S08DZ128CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Package
48LQFP
Family Name
HCS08
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
87
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
24-chx12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ128CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC9S08DV96CLF PDF datasheet
- MC9S08DV96CLF PDF datasheet #2
- MC9S08DZ128CLF PDF datasheet #3
- MC9S08DZ96MLL PDF datasheet #4
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- Download datasheet (5Mb)
13.4.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Freescale Semiconductor
SPPR[2:0]
MODFEN
BIDIROE
SPISWAI
SPR[2:0]
Reset
SPC0
Field
Field
6:4
2:0
4
3
1
0
W
R
SPI Baud Rate Register (SPIxBR)
Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer
to
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
SPI Stop in Wait Mode
0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
divider is the SPI bit rate clock for master mode.
0
0
7
Table 13-2
13-6. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
Table
SPPR2
for more details).
0
6
13-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
Table 13-4. SPIxBR Register Field Descriptions
Table 13-3. SPIxC2 Register Field Descriptions
Figure 13-7. SPI Baud Rate Register (SPIxBR)
MC9S08DZ128 Series Data Sheet, Rev. 1
SPPR1
0
5
SPPR0
0
4
Figure
Description
Description
13-4).
3
0
0
Chapter 13 Serial Peripheral Interface (S08SPIV3)
SPR2
0
2
Figure
13-4). The output of this
SPR1
0
1
SPR0
0
0
315
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