C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 94

• Manufacturer Part Number: C8051F521A-IM
• Description: IC 8051 MCU 8K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F521A-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1490-5

C8051F52x/F52xA/F53x/F53xA
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.1 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, IE, etc.) are bit-addressable
as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR
space are reserved for future use. Accessing these areas will have an indeterminate effect and should be
avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 9.2, for a detailed
description of each register.
Table 9.1. Special Function Register (SFR) Memory Map
94
D8
D0
C8
C0
F8
F0
E8
E0
B8
B0
A8
A0
98
90
88
80
(bit address-
TMR2CN
ADC0CN
PCA0CN
OSCIFIN
SPI0CN
SCON0
TCON
PSW
ACC
able)
0(8)
P1
P0
IP
IE
B
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
REG0CN
REF0CN
CLKSEL
P0MDIN
SBUF0
PCA0L
TMOD
XBR0
1(9)
SP
TMR2RLL TMR2RLH
LINADDR
SPI0CKR
ADC0TK
OSCICN
P1MDIN
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0
ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
ADC0MX
SPI0DAT
LINDATA
CPT0CN
OSCICL
DPH
3(B)
TL1
Rev. 1.3
P0MDOUT P1MDOUT
ADC0CF
P0SKIP
IT01CF
TMR2L
TH0
4(C)
CPT0MD
P1SKIP
TMR2H
ADC0L
LINCF
TH1
5(D)
CKCON
ADC0
EIP1
EIE1
6(E)
VDDMON
RSTSRC
P1MASK
CPT0MX
P0MAT
P1MAT
PSCTL
FLKEY
PCON
7(F)