C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 24

• Manufacturer Part Number: C8051F521A-IM
• Description: IC 8051 MCU 8K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F521A-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1490-5

C8051F52x/F52xA/F53x/F53xA
1.9. Port Input/Output
C8051F52x/F52xA/F53x/F53xA devices include up to 16 I/O pins. Port pins are organized as two byte-
wide ports. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be
configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or
open-drain operation. The “weak pullups” that are fixed on typical 8051 devices may be globally disabled
to save power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip coun-
ter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the
port pins using the Crossbar control registers. This allows the user to select the exact mix of general-pur-
pose port I/O, digital, and analog resources needed for the application.
24
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
T0, T1
P0
P1
UART
CP0
PCA
SPI
LIN
(P0.0-P0.7)
(P1.0-P1.7*)
Figure 1.9. Port I/O Functional Block Diagram
2
2
2
4
7
2
8
8
Rev. 1.3
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
P0MASK, P0MATCH
P1MASK, P1MATCH
Registers
Cells
Cells
I/O
I/O
P0
P1
*Available in
PnMDIN Registers
devices
PnMDOUT,
'F53x/'F53xA
P0.0
P0.7
P1.0*
P1.7*