C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 204

• Manufacturer Part Number: C8051F521A-IM
• Description: IC 8051 MCU 8K FLASH 10DFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F52xr

Specifications of C8051F521A-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 10-DFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1490-5

C8051F52x/F52xA/F53x/F53xA
19.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:





The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 19.3 lists some example timeout intervals for typical
system clocks.
204
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Notes:
System Clock (Hz)
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L
2. Internal oscillator reset frequency.
24,500,000
24,500,000
24,500,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
Table 19.3. Watchdog Timer Timeout Intervals
3,062,500
3,062,500
3,062,500
value of 0x00 at the update time.
191,406
191,406
191,406
32,000
32,000
32,000
2
2
2
PCA0CPL2
Rev. 1.3
255
128
255
128
255
128
255
128
255
128
255
128
32
32
32
32
32
32
Timeout Interval (ms)
24576
12384
129.5
4109
2070
3168
32.1
16.2
42.7
21.5
71.1
35.8
33.1
257
530
4.1
5.5
9.2
1