C8051F521A-IM Silicon Laboratories Inc, C8051F521A-IM Datasheet - Page 23

IC 8051 MCU 8K FLASH 10DFN

C8051F521A-IM

Manufacturer Part Number
C8051F521A-IM
Description
IC 8051 MCU 8K FLASH 10DFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F52xr
Datasheets

Specifications of C8051F521A-IM

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
10-DFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
6
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
6
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1488 - KIT DEV C8051F53XA, C8051F52XA770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1455 - ADAPTER PROGRAM TOOLSTICK F520
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1490-5
1.7. Voltage Regulator
C8051F52x/F52xA/F53x/F53xA devices include an on-chip low dropout voltage regulator (REG0). The
input to REG0 at the V
2.6 V. When enabled, the output of REG0 powers the device and drives the V
can be used to power external devices connected to V
1.8. Serial Port
The C8051F52x/F52xA/F53x/F53xA family includes a full-duplex UART with enhanced baud rate configu-
ration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and
makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
Port I/O
Pins
REGIN
pin can be as high as 5.25 V. The output can be selected by software to 2.1 or
Figure 1.8. Comparator Block Diagram
+
-
VDD
GND
C8051F52x/F52xA/F53x/F53xA
Decision
Reset
Rev. 1.3
Tree
DD
(SYNCHRONIZER)
D
SET
CLR
.
Q
Q
D
SET
CLR
Interrupt
Q
Q
Logic
DD
pin. The voltage regulator
(asynchronous output)
(synchronous output)
CP0A
CP0
23

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