S9S08SG16E1MTJ Freescale Semiconductor, S9S08SG16E1MTJ Datasheet - Page 295

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S9S08SG16E1MTJ

Manufacturer Part Number
S9S08SG16E1MTJ
Description
MCU 16K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of S9S08SG16E1MTJ

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD. POR, PWM, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG16E1MTJ
Manufacturer:
FREESCALE
Quantity:
20 000
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Freescale Semiconductor
ESD Protection and Latch-Up Immunity
1
Latch-up
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Model
Human
Body
No.
1
2
3
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
Human body model (HBM)
Charge device model (CDM)
Latch-up current at T
Table A-5. ESD and Latch-Up Protection Characteristics
Table A-4. ESD and Latch-up Test Conditions
Description
Rating
MC9S08SG32 Data Sheet, Rev. 8
1
A
= 125°C
Symbol
Symbol
V
V
I
R1
HBM
CDM
LAT
C
± 2000
± 500
± 100
Min
Value
1500
– 2.5
100
7.5
3
Appendix A Electrical Characteristics
Max
Unit
Unit
mA
pF
Ω
V
V
V
V
295

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