S9S08SG16E1MTJ Freescale Semiconductor, S9S08SG16E1MTJ Datasheet - Page 179

• Manufacturer Part Number: S9S08SG16E1MTJ
• Description: MCU 16K FLASH 20-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08SG16E1MTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Processor Series: S08SG
• Core: HCS08
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.4
11.4.1
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
11.4.1.1
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
Freescale Semiconductor
FLL Bypassed
External Low
Power(FBELP)
Field
IREFS=0
CLKS=10
BDM Disabled
and LP=1
1
0
Functional Description
Operational Modes
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
FLL Engaged Internal (FEI)
Entered from any state
when MCU enters stop
Table 11-5. ICS Status and Control Register Field Descriptions (continued)
IREFS=0
CLKS=10
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
Figure 11-7. Clock Switching Modes
MC9S08SG32 Data Sheet, Rev. 8
FLL Engaged
External (FEE)
FLL Engaged
Internal (FEI)
IREFS=1
CLKS=00
IREFS=0
CLKS=00
Stop
Description
Chapter 11 Internal Clock Source (S08ICSV2)
FLL Bypassed
Internal (FBI)
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
IREFS=1
CLKS=01
BDM Enabled
or LP=0
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1
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