ST10F272M-4QR3 STMicroelectronics, ST10F272M-4QR3 Datasheet - Page 88

• Manufacturer Part Number: ST10F272M-4QR3
• Description: MCU 16BIT 256K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System reset
20.4
88/176
Figure 24. Synchronous long hardware reset (EA = 0)
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for
2. Minimum RSTIN low pulse duration shall also be longer than 500 ns to guarantee the pulse is not masked
3. 3 to 8 TCL depending on clock source selection.
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, for
example, to leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A software reset is always taken as synchronous: there is no influence on Software Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to the figures
29
for bidirectional.
5 V operation), the asynchronous reset is then immediately entered.
by theinternal filter (refer to
(after filter)
P0[15:13]
RSTOUT
RSTF
P0[12:2]
P0[1:0]
RSTIN
RPD
ALE
RST
≤ 500 ns
≥ 50 ns
4 TCL
25
200 µA discharge
(2)
and
12 TCL
Section
26
Not transparent
≤ 500 ns
≥ 50 ns
for unidirectional SW reset timing, and to figures 27,
21.1).
1024+8 TCL
1024+8 TCL
Not transparent
Transparent
At this time RSTF is sampled LOW
so it is LONG reset
Transparent
≤ 500 ns
≥ 50 ns
3..4 TCL
(1)
3..8 TCL
V
RPD
> 2.5 V asynchronous reset not entered
(3)
Not t.
Not t.
Not t.
8 TCL
ST10F272M
28
and