ST10F272M-4QR3 STMicroelectronics, ST10F272M-4QR3 Datasheet - Page 19

• Manufacturer Part Number: ST10F272M-4QR3
• Description: MCU 16BIT 256K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
Table 1.
RSTOUT
Symbol
RSTIN
V
XTAL3
XTAL4
V
RPD
NMI
V
AGND
V
AREF
V
DD
SS
18
Pin description (continued)
72,82,93
126, 136
127, 139
17, 46,
18,45,
55,71,
83,94,
, 109,
110,
143
144
140
141
142
Pin
37
38
84
56
Type
O
O
I
I
-
-
-
-
-
-
I
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high/low and rise/fall times specified in
the AC characteristics must be observed.
XTAL3 32 kHz oscillator amplifier circuit input
XTAL4 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 must be tied to ground while XTAL4 has to be left open. Additionally, bit
OFF32 in RTCCON register must be set. 32 kHz oscillator can only be driven by
an external crystal, and not by a different clock source.
Reset input with CMOS Schmitt-trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F272M. An
internal pull-up resistor permits power-on reset using only a capacitor connected
to V
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.
Internal reset indication output. This pin is driven to a low level during hardware,
software or watchdog timer reset.
initialization) instruction is executed.
Non-maskable interrupt input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power-down) instruction is executed, the NMI pin must be low in
order to force the ST10F272M to go into power-down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode. If not used, pin NMI should be pulled high externally.
A/D converter reference voltage and analog supply
A/D converter reference and analog ground
Timing pin for the return from interruptible power-down mode and synchronous/
asynchronous reset selection.
Digital supply voltage = +5 V during normal operation, idle and power-down
modes. It can be turned off when stand-by RAM mode is selected.
Digital ground
1.8 V decoupling pin: a decoupling capacitor (typical value of 10 nF, max 100 nF)
must be connected between this pin and nearest V
SS
. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
RSTOUT
Function
remains low until the EINIT (end of
SS
pin.
Pin data
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