ST10F272M-4QR3 STMicroelectronics, ST10F272M-4QR3 Datasheet - Page 132

• Manufacturer Part Number: ST10F272M-4QR3
• Description: MCU 16BIT 256K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
24.7.1
132/176
Table 59.
1. V
2. V
3. Not 100% tested, guaranteed by design characterization
4. During the sample time the input capacitance C
5. This parameter includes the sample time t
6. DNL, INL, OFS and TUE are tested at V
7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not
8. Refer to scheme shown in
Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
V
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting)
can be programmed within a certain range in the ST10F272M relative to the CPU clock. The
absolute time that is consumed by the different conversion steps therefore is independent
from the general speed of the controller. This allows adjustment of the ST10F272M A/D
converter to the system’s properties:
Analog switch resistance
AREF
(approximately 200 µA) on main V
Therefore, it is suggested to maintain the V
switch off the A/D converter circuitry setting bit ADOFF in ADCON register.
these cases will be 0x000
internal resistance of the analog source must allow the capacitance to reach its final voltage level within t
After the end of the sample time t
result. Values for the sample clock t
converter
the result register with the conversion result. Values for the conversion clock t
and can be taken from the next
characterization for all other voltages within the defined voltage range. ‘LSB’ has a value of V
For port5 channels, the specified TUE (± 2 LSB) is guaranteed also with an overload condition (see I
specification) occurring on maximum 2 not selected analog input pins of port5 and the absolute sum of
input overload currents on all Port5 analog input pins does not exceed 10 mA. For port1 channels, the
specified TUE is guaranteed when no overload condition is applied to port1 pins: when an overload
condition occurs on maximum 2 not selected analog input pins of port1 and the input positive overload
current on all analog input pins does not exceed 10 mA (either dynamic or static injection), the specified
TUE is degraded (± 7 LSB). To obtain the same accuracy, the negative injection current on port1 pins must
not exceed -1mA in case of both dynamic and static injection.
selected channels with the overload current within the different specified ranges (for both positive and
negative injection current).
AREF
AIN
pin.
may exceed V
can be tied to ground when A/D converter is not in use. There is increased consumption
Parameter
programming.
A/D converter characteristics (continued)
AGND
(3)(8)
or V
H
Figure
or 0x3FF
AREF
Table
S
40.
DD
, changes of the analog input voltage have no effect on the conversion
up to the absolute maximum ratings. However, the conversion result in
S
R
R
H
due to internal analog circuitry not being completely turned off.
depend on programming and can be taken from
SW
AD
Symbol
, respectively
60.
AREF
S
AREF
, the time for determining the digital result and the time to load
= 5.0 V, V
CC
CC
AIN
at V
can be charged/discharged by the external source. The
DD
Min
AGND
Limit values
–
–
–
level even when not in use, and to eventually
= 0 V, V
1600
1300
Max
600
DD
= 5.0 V. It is guaranteed by design
CC
Unit
W
W
depend on programming
Port5
Port1
Table 60: A/D
Test condition
AREF
ST10F272M
/1024.
OV
S
.