ST10F272M-4QR3 STMicroelectronics, ST10F272M-4QR3 Datasheet - Page 21

• Manufacturer Part Number: ST10F272M-4QR3
• Description: MCU 16BIT 256K FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4QR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
4
Memory organization
The memory space of the ST10F272M is configured in a unified memory architecture. Code
memory, data memory, registers and I/O ports are organized within the same linear address
space of 16 Mbytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFlash: 256 Kbytes of on-chip Flash memory. It is divided in eight blocks (B0F0...B0F7) that
constitute the bank 0. When bootstrap mode is selected, the test-Flash block B0TF
(4 Kbytes) appears at address 00’0000h: refer to
page 25
for IFlash is the following:
Table 2.
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 wordwide (R0
to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 16K + 2K bytes of on-chip extension RAM (single port XRAM) is provided as a
storage for data, user stack and code. The XRAM is divided into two areas, the first 2 Kbytes
named XRAM1 and the second 16 Kbytes named XRAM2, connected to the internal XBUS
and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait
state or read/write delay (50 ns access at 40 MHz CPU clock). Byte and word accesses are
possible.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.
The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit
2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.
for more details on memory mapping in boot mode. The summary of address range
Blocks
B0TF
Summary of IFlash address range
B0F0
B0F1
B0F2
B0F3
B0F4
B0F5
B0F6
B0F7
01’8000h - 01’FFFFh
02’0000h - 02’FFFFh
03’0000h - 03’FFFFh
04’0000h - 04’FFFFh
00’0000h - 00’1FFFh
00’2000h - 00’3FFFh
00’4000h - 00’5FFFh
00’6000h - 00’7FFFh
User mode
Not visible
Chapter 5: Internal Flash memory on
Memory organization
Size (bytes)
32K
64K
64K
64K
4K
8K
8K
8K
8K
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