ST92F124V1QB STMicroelectronics, ST92F124V1QB Datasheet - Page 364
![IC MCU 8BIT 128K MEMORY 100-PQFP](/photos/6/81/68170/497-100-pqfp_series_sml.jpg)
ST92F124V1QB
Manufacturer Part Number
ST92F124V1QB
Description
IC MCU 8BIT 128K MEMORY 100-PQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124V1QB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-QFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
ANALOG TO DIGITAL CONVERTER (Cont’d)
The effect of either of these synchronisation
modes is to set the ST bit by hardware. This bit is
reset, in Single Mode only, at the end of each
group of conversions. In Continuous Mode, all trig-
ger pulses after the first are ignored.
The synchronisation sources must be at a logic
low level for at least the duration of two INTCLK
cycles and, in Single Mode, the period between
trigger pulses must be greater than the total time
required for a group of conversions. If a trigger oc-
curs when the ST bit is still set, i.e. when a conver-
sion is still in progress, it will be ignored.
Note: The external trigger will set the CLR2.ST bit
even if the CLR2.POW is reset.
10.11.3.3 Analog Watchdog
Two internal Analog Watchdogs are available for
highly flexible automatic threshold monitoring of
external analog signal levels. Depending on the
value of the CC[3:0] bits in Control Logic Register1
these two watchdog are mapped onto 2 of the 16
available adjacent channels, allowing the user to
set the channel to be monitored. Refer to
to see the possible choices for this feature.
Analog watchdog channels (named as A and B)
monitor an acceptable voltage level window for the
converted analog inputs. The external voltages
applied to inputs A and B are considered normal
while they remain below their respective Upper
thresholds, and above or at their respective Lower
thresholds.
When the external signal voltage level is greater
than, or equal to, the upper programmed voltage
limit, or when it is less than the lower programmed
voltage limit, a maskable interrupt request is gen-
erated and the Compare Results Register is up-
dated in order to flag the threshold (Upper or Low-
er) and channel (A or B) responsible for the inter-
Figure 157. ADC Trigger Source
364/429
9
Ext. Trigger Enable
Int. Trigger Enable
On-Chip Event
MFT0
ADC Trigger
EXTRG
Software Trigger
Table 68
rupt. The four threshold voltages are user pro-
grammable in dedicated registers pairs (R244 to
R251, page 63). Only the 4 MSBs of the Compare
Results Register are used as flags, each of the
four MSBs being associated with a threshold con-
dition.
Following a reset, these flags are reset. During
normal ADC operation, the CRR bits are set, in or-
der to flag an out of range condition and are auto-
matically reset by hardware after a software reset
of the Analog Watchdog Request flag in the ICR
Register.
10.11.3.4 Power Down Mode
Before enabling an ADC conversion, the POW bit
of the Control Logic Register must be set; this
must be done at least 10 μs before the first conver-
sion start, in order to correctly bias the analog sec-
tion of the converter circuitry.
When the ADC is not required, the POW bit may
be reset in order to reduce the total power con-
sumption. This is the reset configuration, and this
state is also selected automatically when the ST9
is placed in Halt Mode (following the execution of
the halt instruction).
Figure 156. Analog Watchdog Function
Upper Threshold
Lower Threshold
Analog Voltage
Start group of conversions
Continuous or Single mode
(Window Guarded)
Normal Area
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