ST92F124V1QB STMicroelectronics, ST92F124V1QB Datasheet - Page 321
![IC MCU 8BIT 128K MEMORY 100-PQFP](/photos/6/81/68170/497-100-pqfp_series_sml.jpg)
ST92F124V1QB
Manufacturer Part Number
ST92F124V1QB
Description
IC MCU 8BIT 128K MEMORY 100-PQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124V1QB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-QFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.7.2 Stacked Registers
See the description of the OPTIONS register to
obtain more information on the map of the regis-
ters of this section.
JBLPD RECEIVER DMA ADDRESS POINTER
REGISTER (RDAPR)
R252 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = RA[7:1] Receiver DMA Address Pointer.
RDAPR contains the address of the pointer (in the
Register File) of the Receiver DMA data source
when the DMA between the peripheral and the
Memory Space is selected. Otherwise, when the
DMA between the peripheral and Register File is
selected, this register has no meaning.
See
this register.
Bit 0 = PS Memory Segment Pointer Selector.
This bit is set and cleared by software. It is only
meaningful if RDCPR.RF/MEM = 1.
0: The ISR register is used to extend the address
1: The DMASR register is used to extend the ad-
JBLPD
COUNTER REGISTER (RDCPR)
R253 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = RC[7:1] Receiver DMA Counter Pointer.
RDCPR contains the address of the pointer (in the
RA7
RC7
of data received by DMA (see MMU chapter)
dress of data received by DMA (see MMU chap-
ter)
7
7
Section 10.9.6.2
RA6
RC6
RECEIVER
RA5
RC5
RC4
RA4
for more details on the use of
DMA
RC3
RA3
RA2
RC2
TRANSACTION
RA1
RC1
RF/MEM
PS
0
0
J1850 Byte Level Protocol Decoder (JBLPD)
Register File) of the DMA receiver transaction
counter when the DMA between Peripheral and
Memory Space is selected. Otherwise, if the DMA
between Peripheral and Register File is selected,
this register points to a pair of registers that are
used as DMA Address register and DMA Transac-
tion Counter.
See
more details on the use of this register.
Bit 0 = RF/MEM Receiver Register File/Memory
Selector.
If this bit is set to “1”, then the Register File will be
selected as Destination, otherwise the Memory
space will be used.
0: Receiver DMA with Memory space
1: Receiver DMA with Register File
JBLPD TRANSMITTER DMA ADDRESS POINT-
ER REGISTER (TDAPR)
R254 - RSEL[3:0]=0000b
Register Page: 23
Reset Value: xxxx xxxx (xxh)
To select this register, the RSEL[3:0] bits of the
OPTIONS register must be reset
Bit 7:1 = TA[7:1] Transmitter DMA Address Point-
er.
TDAPR contains the address of the pointer (in the
Register File) of the Transmitter DMA data source
when the DMA between the Memory Space and
the peripheral is selected. Otherwise, when the
DMA between Register File and the peripheral is
selected, this register has no meaning.
See
this register.
Bit 0 = PS Memory Segment Pointer Selector.
This bit is set and cleared by software. It is only
meaningful if TDCPR.RF/MEM = 1.
0: The ISR register is used to extend the address
1: The DMASR register is used to extend the ad-
TA7
of data transmitted by DMA (see MMU chapter)
dress of data transmitted by DMA (see MMU
chapter)
7
Section 10.9.6.2
Section
TA6
TA5
10.9.6.1and
TA4
for more details on the use of
TA3
Section 10.9.6.2
TA2
TA1
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