ST92F150CR9TB STMicroelectronics, ST92F150CR9TB Datasheet - Page 344
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ST92F150CR9TB
Manufacturer Part Number
ST92F150CR9TB
Description
IC MCU 8BIT CAN 64K MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CR9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CR9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN MASTER STATUS REGISTER (CMSR)
Reset Value: 0000 0010 (02h)
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 7:4 = Reserved. Forced to 0 by hardware.
Bit 5 = REC Receive
- Read
The CAN hardware is currently receiver.
Bit 4 = TRAN Transmit
- Read
The CAN hardware is currently transmitter.
Bit 3 = WKUI Wake-Up Interrupt
- Read/Clear
This bit is set by hardware to signal that a SOF bit
has been detected while the CAN hardware was in
sleep mode. Setting this bit generates a status
change interrupt if the WKUIE bit in the CIER reg-
ister is set.
This bit is cleared by software.
Bit 2 = ERRI Error Interrupt
- Read/Clear
This bit is set by hardware when a bit of the CESR
has been set on error detection and the corre-
sponding interrupt in the CEIER is enabled. Set-
ting this bit generates a status change interrupt if
the ERRIE bit in the CIER register is set.
This bit is cleared by software.
Bit 1 = SLAK Sleep Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in sleep
mode. This bit acknowledges the sleep mode re-
quest from the software (set SLEEP bit in CMCR
register).
This bit is cleared by hardware when the CAN
hardware has left sleep mode. Sleep mode is left
when the SLEEP bit in the CMCR register is
344/429
9
7
0
0
REC
TRAN WKUI
ERRI
SLAK
INAK
0
cleared. Please refer to the AWUM bit of the
CMCR register description for detailed information
for clearing SLEEP bit.
Bit 0 = INAK Initialization Acknowledge
- Read
This bit is set by hardware and indicates to the
software that the CAN hardware is now in initiali-
zation mode. This bit acknowledges the initializa-
tion request from the software (set INRQ bit in
CMCR register).
This bit is cleared by hardware when the CAN
hardware has left the initialization mode and is
now synchronized on the CAN bus. To be syn-
chronized the hardware has to monitor a se-
quence of 11 consecutive recessive bits on the
CAN RX signal.
CAN TRANSMIT STATUS REGISTER (CTSR)
Read / Write
Reset Value: 0000 0000 (00h)
Note: To clear a bit of this register the software
must write this bit with a one.
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6 = TXOK2 Transmission OK for mailbox 2
- Read
This bit is set by hardware when the transmission
request on mailbox 2 has been completed suc-
cessfully. Please refer to
This bit is cleared by hardware when mailbox 2 is
requested for transmission or when the software
clears the RQCP2 bit.
Bit 5 = TXOK1 Transmission OK for mailbox 1
- Read
This bit is set by hardware when the transmission
request on mailbox 1 has been completed suc-
cessfully. Please refer to
This bit is cleared by hardware when mailbox 1 is
requested for transmission or when the software
clears the RQCP1 bit.
7
0
TXOK2 TXOK1 TXOK0
Figure
Figure
0
RQCP2 RQCP1 RQCP0
147.
147.
0
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