ST92F150CR9TB STMicroelectronics, ST92F150CR9TB Datasheet - Page 118
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ST92F150CR9TB
Manufacturer Part Number
ST92F150CR9TB
Description
IC MCU 8BIT CAN 64K MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CR9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CR9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST92F124/F150/F250 - INTERRUPTS
WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.12.5 Register Description
WAKE-UP CONTROL REGISTER (WUCTRL)
R249 - Read/Write
Register Page: 57
Reset Value: 0000 0000 (00h)
Bit 2 = STOP: Stop bit.
To enter STOP Mode, write the sequence 1,0,1 to
this bit with three consecutive write operations.
When a correct sequence is recognized, the
STOP bit is set and the RCCU puts the MCU in
STOP Mode. The software sequence succeeds
only if the following conditions are true:
– The NMI pin is kept low,
– The WKUP-INT bit is 1,
– All unmasked pending bits are reset
– At least one mask bit is equal to 1 (at least one
Otherwise the MCU cannot enter STOP mode, the
program code continues executing and the STOP
bit remains cleared.
The bit is reset by hardware if, while the MCU is in
STOP mode, a wake-up interrupt comes from any
of the unmasked wake-up lines. The bit is kept
high if, during STOP mode, a rising edge on NMI
pin wakes up the ST9. In this case the user should
reset it by software. The STOP bit is at 1 in the four
following cases (See “Wake-up Mode Selection”
on page 114. for details):
– After the first write instruction of the sequence (a
– At the end of a successful sequence (i.e. after
– The ST9 entered and exited STOP mode due to
– The ST9 did not enter STOP mode due to the
Note: The STOP request generated by the
WUIMU (that allows the ST9 to enter STOP mode)
is ORed with the external STOP pin (active low).
This means that if the external STOP pin is forced
118/429
9
external wake-up line is not masked).
7
-
1 is written to the STOP bit)
the third write instruction of the sequence)
a rising edge on the NMI pin. In this case the
EX_STP bit in the CLK_FLAG is at 1 (see
RCCU chapter).
NMI pin being kept high. In this case RCCU bit
EX_STP is at 0
-
-
-
-
STOP
ID1S
WKUP-INT
0
low, the ST9 will enter STOP mode independently
of the status of the STOP bit.
WARNINGS:
– Writing the sequence 1,0,1 to the STOP bit will
– Whenever a STOP request is issued to the MCU,
Bit 1 = ID1S: Interrupt Channel INTD1 Source.
This bit is set and cleared by software.
It enables the 16 wake-up lines as external inter-
rupt sources. This bit must be set to 1 to enable
the wake-up lines.
WARNING: To avoid spurious interrupt requests
on the INTD1 channel due to changing the inter-
rupt source, use this procedure to modify the ID1S
bit:
1. Mask the INTD1 interrupt channel (bit 7 of reg-
2. Set the ID1S bit.
3. Clear the IPD1 interrupt pending bit (bit 7 of
4. Remove the mask on INTD1 (bit EIMR.7=1).
Bit 0 = WKUP-INT: Wakeup Interrupt.
This bit is set and cleared by software.
0: The 16 external wakeup lines can be used to
1: The 16 external wake-up lines to work as wake-
enter STOP mode only if no other register write
instructions are executed during the sequence. If
Interrupt or DMA requests (which always perform
register write operations) are acknowledged dur-
ing the sequence, the ST9 will not enter STOP
mode: the user must re-enter the sequence to
set the STOP bit.
a few clock cycles are needed to enter STOP
mode (see RCCU chapter for further details).
Hence the execution of the instruction following
the STOP bit setting sequence might start before
entering STOP mode: if such instruction per-
forms a register write operation, the ST9 will not
enter in STOP mode. In order to avoid to execute
register write instructions after a correct STOP
bit setting sequence and before entering the
STOP mode, it is mandatory to execute 3 NOP
instructions after the STOP bit setting sequence.
Refer to
generate interrupt requests
up sources for exiting from STOP mode
ister EIMR - R244, Page 0 - reset to 0).
register EIPR - R243, Page 0)
Section 13.2 on page
409.
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