ST92F150CR9TB STMicroelectronics, ST92F150CR9TB Datasheet - Page 189
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ST92F150CR9TB
Manufacturer Part Number
ST92F150CR9TB
Description
IC MCU 8BIT CAN 64K MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CR9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CR9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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MULTIFUNCTION TIMER (Cont’d)
The configuration of each input is programmed in
the Input Control Register.
Each of the two output pins can be driven from any
of three possible sources:
– Compare Register 0 logic
– Compare Register 1 logic
– Overflow/Underflow logic
Each of these three sources can cause one of the
following four actions, independently, on each of
the two outputs:
– Nop, Set, Reset, Toggle
In addition, an additional On-Chip Event signal can
be generated by two of the three sources men-
tioned above, i.e. Over/Underflow event and Com-
pare 0 event. This signal can be used internally to
Figure 102. Detailed Block Diagram
synchronise another on-chip peripheral. Five
maskable interrupt sources referring to an End Of
Count condition, 2 input captures and 2 output
compares, can generate 3 different interrupt re-
quests (with hardware fixed priority), pointing to 3
interrupt routine vectors.
Two independent DMA channels are available for
rapid data transfer operations. Each DMA request
(associated with a capture on the REG0R register,
or with a compare on the CMP0R register) has pri-
ority over an interrupt request generated by the
same source.
A SWAP mode is also available to allow high
speed continuous transfers (see Interrupt and
DMA chapter).
MULTIFUNCTION TIMER (MFT)
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