ST92F150CR9TB STMicroelectronics, ST92F150CR9TB Datasheet - Page 268
![IC MCU 8BIT CAN 64K MEM 64-LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
ST92F150CR9TB
Manufacturer Part Number
ST92F150CR9TB
Description
IC MCU 8BIT CAN 64K MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CR9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CR9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
- Current page: 268 of 429
- Download datasheet (8Mb)
I2C BUS INTERFACE
I
Figure 128. Transfer Sequencing
10-bit Master transmitter
Legend:
S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
EVx=Event (with interrupt if ITE=1)
268/429
9
2
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master receiver:
S Address
S Address
S Header
S
S
S
C BUS INTERFACE (Cont’d)
EV5
EV5
EV5
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the
lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by
STOP=1, STOP=0 the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
Address
Address
Header
is complete.
is complete.
A
A
A
EV1
EV1 EV3
Address
A
A
A
Data1
EV6
EV6 EV8
EV9
A
Data1
Address
S
Data1
S
r
r
EV1
EV5
A
Header A
Data1
EV2
Data1
A
Header
A
A
Data2
EV3
EV7
EV6 EV8
A
EV1 EV3
A
Data2
EV8
A
Data2
EV2
EV6
A
Data2
Data1
EV2
Data1
A
.....
A
Data1
EV3
EV7
DataN
.....
A
A
A
EV8
EV8
A
DataN
.....
.....
EV3
EV7
A
DataN
.....
.....
DataN
....
.
EV2
.....
A
DataN
DataN
DataN
EV2
P
NA
NA
DataN
EV4
A
P
EV3-1
EV7
A
A
EV3-1
EV4
A
EV8
EV8
P
P
EV7
P
EV4
P
P
EV4
P
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