ST92F150CR9TB STMicroelectronics, ST92F150CR9TB Datasheet - Page 302
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ST92F150CR9TB
Manufacturer Part Number
ST92F150CR9TB
Description
IC MCU 8BIT CAN 64K MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CR9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CR9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
- Current page: 302 of 429
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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
10.9.6.4 DMA Management in Transmission
Mode
DMA in transmission is performed when the TRDY
bit of the STATUS register is set (by hardware).
The TRDY bit is reset as soon as the DMA cycle is
finished.
To enable the DMA feature, the TXD_M bit in the
IMR register must be set (by software).
Compared to reception, in transmission each DMA
request performs the transfer of either a single
byte or a couple of bytes depending on the value
of the Transmit Opcode bits (TXOP.OP[2:0]) writ-
ten during the DMA transfer.
The table of values managed by the DMA must be
a sequence of opcode bytes (that will be written in
the TXOP register by the DMA) each one followed
by a data byte (that will be written in the TXDATA
register by the DMA) if the opcode needs it (see
Figure
Each DMA cycle consists of the following transfers
for a total of three/six operations that are per-
formed with minimum use of CPU time:
– A load to the JBLPD Transmit Opcode register
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
and if the Transmit Opcode placed in TXOP re-
quires a datum:
– A load to the peripheral data register (TXDATA)
302/429
9
(TXOP) from a location of Register File/Memory
addressed through the DMA Address Register
(or Register pair);
(or Register pair);
ter, which contains the number of transactions
that have still to be performed;
from a location of Register File/Memory ad-
dressed through the DMA Address Register (or
140).
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
Note: When the TEOBP pending bit is set (at the
end of the last DMA transfer), the transmission
DMA enable bit (TXD_M) is automatically reset by
hardware. However, the DMA can be disabled by
software resetting the TXD_M bit.
Note: When using DMA, the TXOP byte is written
before the TXDATA register. This order is accept-
ed by the JBLPD only when the DMA in transmis-
sion is enabled.
Note: The DMA request acknowledge could de-
pend on the priority level stored in the PRLR regis-
ter. In the same way, some time can occur be-
tween the transfer of the first byte and the transfer
of the second one if another interrupt or DMA re-
quest with higher priority occurs.
10.9.6.5 DMA Suspend mode
In the JBLPD it is possible to suspend or not to
suspend the DMA transfer while some J1850 pro-
tocol events occur. The selection between the two
modes is done by programming the DMASUSP bit
of the OPTIONS register.
If the DMASUSP bit is set (DMA suspended
mode), while the ERROR or TLA flag is set, the
DMA transfers are suspended, to allow the user
program to handle the event condition.
If the DMASUSP bit is reset (DMA not suspended
mode), the previous flags have no effect on the
DMA transfers.
Register pair); it is the next location in the TX-
DATA transfer cycle;
(or Register pair);
ter, which contains the number of transactions
that have still to be performed.
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