ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 337
![IC MCU 8BIT 64K MEMORY 64-LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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CONTROLLER AREA NETWORK (Cont’d)
10.10.5.5 Message Storage
The interface between the software and the hard-
ware for the CAN messages is implemented by
means of mailboxes. A mailbox contains all infor-
mation related to a message; identifier, data, con-
trol, status and time stamp information.
Transmit Mailbox
The software sets up the message to be transmit-
ted in an empty transmit mailbox. The status of the
transmission is indicated by hardware in the
MCSR register.
Offset to Transmit
Mailbox base ad-
dress (bytes)
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Transmit Mailbox Mapping
Register Name
MCSR
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSR0
MTSR1
CONTROLLER AREA NETWORK (bxCAN)
Receive Mailbox
When a message has been received, it is available
to the software in the FIFO output mailbox. Once
the software has handled the message (e.g. read
it) the software must release the FIFO output mail-
box by means of the RFOM bit in the CRFR regis-
ter to make the next incoming message available.
The filter match index is stored in the MFMI regis-
ter. The 16-bit time stamp value is stored in the
MTSR[0:1] registers.
Offset to Receive
Mailbox base ad-
dress (bytes)
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Receive Mailbox Mapping
Register Name
MFMI
MDLC
MIDR0
MIDR1
MIDR2
MIDR3
MDAR0
MDAR1
MDAR2
MDAR3
MDAR4
MDAR5
MDAR6
MDAR7
MTSR0
MTSR1
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