ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 126
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ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)
7 RESET AND CLOCK CONTROL UNIT (RCCU)
7.1 INTRODUCTION
The Reset and Clock Control Unit (RCCU) com-
prises two distinct sections:
– the Clock Control Unit, which generates and
– the Reset/Stop Manager, which detects and
On ST9 devices where the external Stop pin and/
or the Wake-Up Interrupt Manager Unit are availa-
ble, this circuit also detects and manages the Stop
mode during which all oscillators are frozen in or-
der to achieve the lowest possible power con-
sumption (refer to the Reset/Stop mode and
Wake-Up Interrupt Manager Unit description).
7.2 CLOCK CONTROL UNIT
The Clock Control Unit generates the internal
clocks for the CPU core (CPUCLK) and for the on-
chip peripherals (INTCLK). The Clock Control Unit
may be driven by the on-chip oscillator (provided
an external crystal circuit is connected to the OS-
CIN and OSCOUT pins), or by an external pulse
generator, connected to OSCOUT (see
and
is required, a low frequency external clock may be
selected. To do this, this clock source must be
connected to the CK_AF pin.
7.2.1 Clock Control Unit Overview
As shown in
can divide the CLOCK1 input clock signal by two.
In practice, the divide-by-two is virtually always
used in order to ensure a 50% duty cycle signal to
Figure 59. Clock Control Unit Simplified Block Diagram
126/429
9
manages the internal clock signals.
flags Hardware, Software and Watchdog gener-
ated resets.
oscillator
CK_AF
source
Crystal
Figure
CLOCK1
CK_AF
68). When significant power reduction
Figure 59
1/2
a programmable divider
CLOCK2
Clock Multiplier
/Divider
Figure 66
1/16
PLL
Unit
the PLL multiplier circuit. The resulting signal,
CLOCK2, is the reference input clock to the pro-
grammable Phase Locked Loop frequency multi-
plier, which is capable of multiplying the clock fre-
quency by a factor of 6, 8, 10 or 14; the multiplied
clock is then divided by a programmable divider,
by a factor of 1 to 7. By these means, the ST9 can
operate with cheaper, medium frequency (3-5
MHz) crystals, while still providing a high frequen-
cy internal clock for maximum system perform-
ance; the range of available multiplication and divi-
sion factors allow a great number of operating
clock frequencies to be derived from a single crys-
tal frequency.
For low power operation, especially in Wait for In-
terrupt mode, the Clock Multiplier unit may be
turned off, whereupon the output clock signal may
be programmed as CLOCK2 divided by 16. For
further power reduction, a low frequency external
clock connected to the CK_AF pin may be select-
ed, whereupon the crystal controlled main oscilla-
tor may be turned off.
The internal system clock, INTCLK, is routed to all
on-chip peripherals, as well as to the programma-
ble Clock Prescaler Unit which generates the clock
for the CPU core (CPUCLK). (See
The Clock Prescaler is programmable and can
slow the CPU clock by a factor of up to 8, allowing
the programmer to reduce CPU processing speed,
and thus power consumption, while maintaining a
high speed clock to the peripherals. This is partic-
ularly useful when little actual processing is being
done by the CPU and the peripherals are doing
most of the work.
CPU Clock
Prescaler
Figure
Peripherals
CPU Core
CPUCLK
INTCLK
to
59)
to
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