ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 208
![IC MCU 8BIT 64K MEMORY 64-LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
FLAG REGISTER (T_FLAGR)
R254 - Read/Write
Register Page: 10
Reset value: 0000 0000 (00h)
Bit 7 = CP0: Capture 0 flag.
This bit is set by hardware after a capture on
REG0R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP0 bit must be cleared by software.
Setting by software acts as a software load/cap-
ture to/from the REG0R register.
0: No Capture 0 event
1: Capture 0 event occurred
Bit 6 = CP1: Capture 1 flag.
This bit is set by hardware after a capture on
REG1R register. An interrupt is generated de-
pending on the value of the GTIEN, CP0I bits in
the IDMR register and the A0 bit in the T_FLAGR
register. The CP1 bit must be cleared by software.
Setting by software acts as a capture event on the
REG1R register, except when in Bicapture mode.
0: No Capture 1 event
1: Capture 1 event occurred
Bit 5 = CM0: Compare 0 flag.
This bit is set by hardware after a successful com-
pare on the CMP0R register. An interrupt is gener-
ated if the GTIEN and CM0I bits in the IDMR reg-
ister are set. The CM0 bit is cleared by software.
0: No Compare 0 event
1: Compare 0 event occurred
Bit 4 = CM1: Compare 1 flag.
This bit is set after a successful compare on
CMP1R register. An interrupt is generated if the
208/429
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CP0 CP1 CM0 CM1 OUF
7
OCP0
OCM0 A0
0
GTIEN and CM1I bits in the IDMR register are set.
The CM1 bit is cleared by software.
0: No Compare 1 event
1: Compare 1 event occurred
Bit 3 = OUF: Overflow/Underflow.
This bit is set by hardware after a counter Over/
Underflow condition. An interrupt is generated if
GTIEN and OUI=1 in the IDMR register. The OUF
bit is cleared by software.
0: No counter overflow/underflow
1: Counter overflow/underflow
Bit 2 = OCP0: Overrun on Capture 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CP0 flag is
cleared by software or whenever a capture is sim-
ulated by setting the CP0 flag by software. The
OCP0 flag is cleared by software.
0: No capture 0 overrun
1: Capture 0 overrun
Bit 1 = OCM0: Overrun on compare 0.
This bit is set by hardware when more than one
INT/DMA requests occur before the CM0 flag is
cleared by software.The OCM0 flag is cleared by
software.
0: No compare 0 overrun
1: Compare 0 overrun
Bit 0 = A0: Capture interrupt function.
This bit is set and cleared by software.
0: Configure the capture interrupt as an OR func-
1: Configure the capture interrupt as an AND func-
Note: When A0 is set, both CP0I and CP1I in the
IDMR register must be set to enable both capture
interrupts.
tion of REG0R/REG1R captures
tion of REG0R/REG1R captures
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