ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 257
![IC MCU 8BIT 64K MEMORY 64-LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPSR register while the
2. A write to the SPCR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPOE and MSTR
– The MODF bit is set and an SPI interrupt is
– The SPOE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the device
generated if the SPIE bit is set.
from the device and disables the SPI periph-
eral.
into slave mode.
MODF bit is set.
bits may be restored to their original state during or
after this clearing sequence.
Hardware does not allow the user to set the SPOE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
10.7.4.6 Overrun Condition
An overrun condition occurs, when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPDR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripher-
al.
SERIAL PERIPHERAL INTERFACE (SPI)
257/429
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