ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 263
![IC MCU 8BIT 64K MEMORY 64-LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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I
Figure 126. I
10.8.3 Functional Description
Refer to the I2CCR, I2CSR1 and I2CSR2 registers
in
The I
between the ST9 microcontroller and the I
protocol. In addition to receiving and transmitting
data, the interface converts data from serial to
parallel format and vice versa using an interrupt or
polled handshake.
It operates in Multimaster/slave I
lection of the operating mode is made by software.
The I
data pin (SDA) and a clock pin (SCL) which must
be configured as open drain when the I
enabled by programming the I/O port bits and the
PE bit in the I2CCR register. In this case, the value
of the external pull-up resistance used depends on
the application.
When the I
ports revert to being standard I/O port pins.
2
C BUS INTERFACE (Cont’d)
Section
2
2
C interface is connected to the I
C interface works as an I/O interface
SCL
SDA
10.8.7. for the bit definitions.
2
C cell is disabled, the SDA and SCL
2
C Interface Block Diagram
DMA
CONTROL
CONTROL
CLOCK
DATA
CONTROL SIGNALS
2
C mode. The se-
2
C bus by a
2
C cell is
2
C bus
LOGIC AND INTERRUPT/DMA REGISTERS
CLOCK CONTROL REGISTER
OWN ADDRESS REGISTER 2
OWN ADDRESS REGISTER 1
GENERAL CALL ADDRESS
DATA SHIFT REGISTER
STATUS REGISTER 1
STATUS REGISTER 2
CONTROL REGISTER
DATA BUS
The I
Six of them are used for initialization:
– Own Address Registers I2COAR1, I2COAR2
– General Call Address Register I2CADR
– Clock Control Registers I2CCCR, I2CECCR
– Control register I2CCR
The following four registers are used during data
transmission/reception:
– Data Register I2CDR
– Control Register I2CCR
– Status Register 1 I2CSR1
– Status Register 2 I2CSR2
DATA REGISTER
COMPARATOR
2
C interface has sixteen internal registers.
INTERRUPT
I2C BUS INTERFACE
VR02119A
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