ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 317
![IC MCU 8BIT 64K MEMORY 64-LQFP](/photos/12/15/121504/stmicroelectronics-64-lqfp_sml.jpg)
ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
- Current page: 317 of 429
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 4 = SLP Receiver Sleep Mode.
The SLP bit is written to one when the user pro-
gram does not want to receive any data from the
JBLPD VPWI pin until an EOFM symbol occurs.
This mode is usually set when a message is re-
ceived that the user does not require - including
messages that the JBLPD is transmitting.
If the JBLPD is not transmitting and is in Sleep
mode, no data is transferred to the RXDATA regis-
ter, the RDRF flag does not get set, and errors as-
sociated with received data (RDOF, CRCE, IFD,
IBD) do not get set. Also, the EODM flag will not
get set.
If the JBLPD peripheral is transmitting and is in
sleep mode, no data is transferred to the RXDATA
register, the RDRF flag does not get set and the
RDOF error flag is inhibited. The CRCE, IFD, and
IBD flags, however, will NOT be inhibited while
transmitting in sleep mode.
The SLP bit cannot be written to zero by the user
program. The SLP bit is set on reset or TTO get-
ting set, and it will stay set upon JE getting set until
an EOFM symbol is received.
The SLP gets cleared on reception of an EOF or a
Break symbol. SLP is set while CONTROL.JE is
reset and while CONTROL.JDIS is set.
0: The JBLPD is not in Sleep Mode
1: The JBLPD is in Sleep Mode
Bit 3:2 = Reserved.
Bit 1 = REOP Receiver DMA End Of Block Pend-
ing.
This bit is set after a receiver DMA cycle to mark
the end of a block of data. An interrupt request is
performed if the RDRF_M bit of the IMR register is
set. REOBP should be reset by software in order
to avoid undesired interrupt routines, especially in
initialisation routine (after reset) and after entering
the End Of Block interrupt routine.
Writing “0” in this bit will cancel the interrupt re-
quest.
This bit is reset when the CONTROL.JDIS bit is
set at least for 6 MCU clock cycles (3 NOPs).
Note: When the REOBP flag is set, the RXD_M bit
is reset by hardware.
Note: REOBP can only be written to “0”.
Bit 0 = TEOP Transmitter DMA End Of Block
Pending.
This bit is set after a transmitter DMA cycle to mark
J1850 Byte Level Protocol Decoder (JBLPD)
the end of a block of data. An interrupt request is
performed if the TRDY_M bit of the IMR register is
set. TEOBP should be reset by software in order to
avoid undesired interrupt routines, especially in in-
itialisation routine (after reset) and after entering
the End Of Block interrupt routine.
Writing “0” in this bit will cancel the interrupt re-
quest.
This bit is reset when the CONTROL.JDIS bit is
set at least for 6 MCU clock cycles (3 NOPs).
Note: When the TEOBP flag is set, the TXD_M bit
is reset by hardware.
Note: TEOBP can only be written to “0”.
JBLPD INTERRUPT MASK REGISTER (IMR)
R250 - Read/Write
Register Page: 23
Reset Value: 0000 0000 (00h)
To enable an interrupt source to produce an inter-
rupt request, the related mask bit must be set.
When these bits are reset, the related Interrupt
Pending bit can not generate an interrupt.
Note: This register is forced to its reset value if the
CONTROL.JDIS bit is set at least for 6 clock cy-
cles (3 NOPs). If the JDIS bit is set for a shorter
time, the bits could be reset or not reset.
Bit 7 = ERR_M Error Interrupt Mask bit.
This bit enables the “error” interrupt source to gen-
erate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: Error interrupt source masked
1: Error interrupt source un-masked
Bit 6 = TRDY_M Transmit Ready Interrupt Mask
bit.
This bit enables the “transmit ready” interrupt
source to generate an interrupt request.
This bit is reset if the CONTROL.JDIS bit is set at
least for 6 clock cycles (3 NOPs).
0: TRDY interrupt source masked
1: TRDY interrupt source un-masked
ERR_
M
7
TRDY_
M
RDRF_
M
TLA_
M
RXD_
M
EODM_
M
EOFM_
M
317/429
TXD_
M
0
9
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