ST92F124R9TB STMicroelectronics, ST92F124R9TB Datasheet - Page 104
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ST92F124R9TB
Manufacturer Part Number
ST92F124R9TB
Description
IC MCU 8BIT 64K MEMORY 64-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F124R9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
I²C, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Processor Series
ST92F12x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
6 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F124R9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST92F124/F150/F250 - INTERRUPTS
5.7.2 IMPORTANT NOTE ON STANDARD
INTERRUPTS
Refer to
5.8 TOP LEVEL INTERRUPT
The Top Level Interrupt channel can be assigned
either to the external pin NMI or to the Timer/
Watchdog according to the status of the control bit
EIVR.TLIS (R246.2, Page 0). If this bit is high (the
reset condition) the source is the external pin NMI.
If it is low, the source is the Timer/ Watchdog End
Of Count. When the source is the NMI external
pin, the control bit EIVR.TLTEV (R246.3; Page 0)
selects between the rising (if set) or falling (if reset)
edge generating the interrupt request. When the
selected event occurs, the CICR.TLIP bit (R230.6)
is set. Depending on the mask situation, a Top
Level Interrupt request may be generated. Two
kinds of masks are available, a Maskable mask
and a Non-Maskable mask. The first mask is the
CICR.TLI bit (R230.5): it can be set or cleared to
enable or disable respectively the Top Level Inter-
rupt request. If it is enabled, the global Enable In-
terrupt bit, CICR.IEN (R230.4) must also be ena-
bled in order to allow a Top Level Request.
The second mask NICR.TLNM (R247.7) is a set-
only mask. Once set, it enables the Top Level In-
terrupt request independently of the value of
CICR.IEN and it cannot be cleared by the pro-
gram. Only the processor RESET cycle can clear
this bit. This does not prevent the user from ignor-
ing some sources due to a change in TLIS.
The Top Level Interrupt Service Routine cannot be
interrupted by any other interrupt or DMA request,
in any arbitration mode, not even by a subsequent
Top Level Interrupt request.
104/429
9
Section 13.4 on page
413.
Warning. The interrupt machine cycle of the Top
Level Interrupt does not clear the CICR.IEN bit,
and the corresponding iret does not set it. Fur-
thermore the TLI never modifies the CPL bits and
the NICR register.
5.9
INTERRUPTS
Some of the on-chip peripherals have their own
specific interrupt unit containing one or more inter-
rupt channels, or DMA channels. Please refer to
the specific peripheral chapter for the description
of its interrupt features and control registers.
The on-chip peripheral interrupts are controlled by
the following bits:
– Interrupt Pending bit (IP). Set by hardware
– Interrupt Mask bit (IM). If IM = “0”, no interrupt
– Priority Level (PRL, 3 bits). These bits define
– Interrupt Vector Register (IVR, up to 7 bits).
when the Trigger Event occurs. Can be set/
cleared by software to generate/cancel pending
interrupts and give the status for Interrupt polling.
request is generated. If IM =“1” an interrupt re-
quest is generated whenever IP = “1” and
CICR.IEN = “1”.
the current priority level, PRL=0: the highest pri-
ority, PRL=7: the lowest priority (the interrupt
cannot be acknowledged)
The IVR points to the vector table which itself
contains the interrupt routine start address.
DEDICATED
ON-CHIP
PERIPHERAL
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