Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 350

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 181. Oscillator Divide Register (OSCDIV)
BITS
FIELD
RESET
R/W
ADDR
* The reset value is 08H if the option bit LPOPT is 0.
PS022008-0810
Bit Position
[3]
WDFEN
[2]
FLPEN
[1:0]
SCKSEL
Bit Position
[7:0]
DIV
Oscillator Divide Register
00H to FFH
7
Value (H) Description
Value (H)
The Oscillator Divide register (OSCDIV) provides the value to divide the system clock by.
The Oscillator Divide register must be unlocked before writing. Writing the two-step
sequence
The register locks after completion of a register write to the OSCDIV.
00
01
10
11
0
1
0
1
E7H
6
Oscillator Divide
00H - divider is disabled, all other entries are the divide value for scaling the
system clock.
Description
WDT Oscillator Failure Detection Enable
Failure detection of WDT oscillator is disabled.This bit is
automatically if a WDT oscillator failure is detected.
Failure detection of WDT oscillator is enabled.
Flash Low Power Mode Enable
Flash Low Power Mode is disabled.
Flash Low Power Mode is enabl ed. The Flash will be powered down during
idle periods of the clock and powered up during Flash reads. This bit must
only be set if the frequency of the primary oscillator source is 8 MHz or lower.
The reset value of this bit is controlled by the LPOPT option bit during reset.
System Clock Oscillator Select
Internal precision oscillator functions as system clock at 5.6 MHz.
Crystal oscillator or external clock driver functions as system clock.
Reserved.
Watchdog Timer oscillator functions as system clock.
followed by
5
P R E L I M I N A R Y
18H
to the Oscillator Control register address unlocks it.
4
FF_E0A1H
00H*
R/W
DIV
3
2
Product Specification
ZNEO
1
Oscillator Control
Z16F Series
cleared
0
334