Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 232

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PS022008-0810
10. The I
11. The I
12. Software responds by setting the
13. Software responds by writing
14. If you want to read only one byte, software responds by setting the
15. After the I
16. The I
17. The I
18. The I
19. The I
20. The I
21. The I
22. Software responds by reading the I
23. The I
24. If there are more bytes to transfer, the I
25. The I
the STOP condition on the bus and clears the
complete (ignore the following steps).
register (lower byte of 10 bit address).
I
repeated Start.
(read) to the I
Control register.
transfer), the I
the next High period of SCL. 

If the slave does not acknowledge the address byte, the I
bit in the I
register. Software responds to the Not Acknowledge interrupt by setting the STOP bit
and clearing the TXI bit. The I
the STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
register (third address transfer).
Slave read address and a 1 (read).
High period of SCL.
last, software must set the
based on the
2
C Controller generates a Transmit interrupt.
2
2
2
2
2
2
2
2
2
2
C Controller shifts out the next eight bits of address. After the first bit shifts, the
C Controller loads the I
C Controller sends the repeated START condition.
C Controller loads the I
C Controller sends
C Slave sends an acknowledge by pulling the SDA signal Low during the next
C Controller shifts in a byte of data from the Slave.
C Controller asserts the Receive interrupt.
C Controller sends an Acknowledge or Not Acknowledge to the I
C Controller generates a NAK interrupt (NCKI bit in I2CISTAT).
2
2
C Status register, sets the ACKV bit and clears the
C Controller shifts out the address bits mentioned in step 9 (second address
NAK
2
2
C Data register.
C Slave sends an acknowledge by pulling the SDA signal Low during
bit.
P R E L I M I N A R Y
11110B
NAK
2
11110B
2
2
C Shift register with the contents of the I
C Shift register with the contents of the I
bit of the I
C Controller flushes the transmit data register, sends
START
followed by the two most significant bits of the
2
C Data register. If the next data byte is to be the
followed by the 2-bit Slave address and a 1
2
C Controller returns to step 18.
bit of the I
2
C Control register.
STOP
2
and
C Control register to generate a
NCKI
2
C Controller sets the
I
2
C Master/Slave Controller
Product Specification
bits. The transaction is
ACK
ZNEO
bit in the I
NAK
Z16F Series
2
2
2
bit of the I
C Data
C Data
C Slave
2
C State
NCKI
2
C
216