Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 239

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PS022008-0810
DMA Control of I
6. Software responds to the interrupt by reading the I2CISTAT register, clearing the
7. The Master starts the data transfer by asserting SCL Low. Once the I
8. When the first bit of the first data byte is transferred, the I
9. Software responds to the transmit data interrupt by loading the next data byte into the
10. The I
11. The bus cycles through steps 7–10 until the last byte has been transferred. If software
12. Software responds to the NAK interrupt by clearing the
13. When the Master has completed the acknowledge cycle of the last transfer it asserts
14. The Slave I
15. Software responds to the Stop interrupt by reading the I2CISTAT register, clearing the
The DMA engine is configured to support transmit and receive DMA requests from the
I
in the I
error condition interrupts to be handled by software while data movement is handled by
the DMA engine.
The DMA interface on the I
master mode address byte transfer. The START, STOP, and NAK bits must be controlled
by software.
2
C Controller. The I
I2CISTAT register, which causes the Slave Address Match interrupt. The
= 1. The Slave mode I
bit. Software loads the initial data byte into the I2CDATA register and sets the
in the I2CCTL register.
data available to transmit the SCL is released and the Master proceeds to shift the first
data byte.
bit, which asserts the transmit data interrupt.
I2CDATA register.
Acknowledge (or Not Acknowledge for the last data byte).
has not yet loaded the next data byte when the Master brings SCL Low to transfer the
most significant data bit, the Slave I
register is written.
When the Slave receives a Not Acknowledge, the I
the I2CISTAT register and generates the NAK interrupt.
register and by asserting the
the STOP or RESTART condition on the bus.
I2CISTAT register).
SPRS
2
C Mode register and clearing the TXI bit in the I
2
bit.
C Master shifts in the remainder of the data byte. The Master transmits the
2
C Transactions
2
C Controller asserts the STOP/RESTART interrupt (set
2
C data interrupt requests must be disabled by setting the
2
P R E L I M I N A R Y
C Controller acknowledges on the bus.
2
C Controller is intended to support data transfer but not
FLUSH
2
bit of the I2CCTL register.
C Controller holds SCL Low until the data
2
C Controller sets the
2
C Control register. This allows
TXI
2
I
C controller sets the
2
C Master/Slave Controller
Product Specification
bit in the I2CCTL
ZNEO
2
SPRS
C Controller has
Z16F Series
NCKI
RD
DMAIF
bit in
bit is set
TXI
bit in
TDRE
SAM
bit
bit
223