Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 287

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PS022008-0810
DMA Control Bit Definitions
Table 141. Linked list Descriptor
The following paragraphs explain the control bits of each DMA channel.
DMAxEN
This bit if set by the CPU enables the DMA channel for direct operation. Direct operation
uses the addresses and transfer length, which has been directly written to the DMA 
Channel by software.
If this bit is set by a descriptor read then linked list mode is enabled. Linked list operation
starts when an address is written to the DMAxLAR. This write causes the DMA to read in
the descriptor control value and addresses and place them in the DMA Channel.
LOOP
If the DMA is in linked list mode and this bit is set to one, it prevents the DMA from
updating the descriptor when the buffer is closed. This bit is set to allow lists to loop on
themselves without software intervention.
TXSIZE
The TXSIZE bits sets the width of the transfer.
00 = 8-bit bytes are transferred on each DMA transfer. The destination and source
addresses increment or decrement by one for each transfers if the DSTCTL and/or SRC-
CTL is selected for increment or decrement. The transfer length is decremented by one.
This allows 64 Kbytes to be transferred.
01 = A 16-bit word is transferred on each DMA transfer. The destination and source
addresses increment or decrement by two if the DSTCTL and/or SRCCTL is selected for
increment or decrement. In word mode the transfer length is still decremented by one. This
allows 64 Kwords to be transferred.
10 = A 32-bit quad is transferred on each DMA transfer. The destination and source
addresses increment or decrement by four if the DSTCTL and/or SRCCTL is selected for
Address
LAR
LAR + 02H
LAR + 04H
LAR + 08H
LAR + 0CH
LAR High
Even
CONTROL
TXLN
DAR High
SAR High
P R E L I M I N A R Y
Product Specification
ZNEO
DMA Controller
Z16F Series
271