Z16F2810FI20EG Zilog, Z16F2810FI20EG Datasheet - Page 317

• Manufacturer Part Number: Z16F2810FI20EG
• Description: IC ZNEO MCU FLASH 128K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810FI20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-BQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PS022008-0810
Serial Data Format
The data format of the serial interface uses the asynchronous protocol defined in RS-232.
Each character is transmitted as 1 start bit, 8-9 data bits (least-significant bit first), and 
1 stop bit (see
Each bit time is of same length. The bit period is set by the baud rate generator.
When the transmitter sends a character, it first sends a Low start bit. The transmitter then
waits one bit time. After the start bit is sent, the transmitter sends the next data bit. The
transmitter sends each data bit in turn, waiting one full bit time before sending the next
data bit. After the last data bit is sent, the transmitter sends a high stop bit for one bit time.
The receiver looks for the falling edge of the start bit. Once the receiver sees the start bit 
is Low, it waits one half bit time and samples the middle of the start bit. If the middle of
the start bit is High, the receiver considers this as a false start bit. The receiver ignores a
false start bit and searches for another falling edge. If the middle of the start bit is Low, the
receiver considers the start bit valid. The receiver will wait a full bit time from the middle
of the start bit to sample the next data bit. The next data bit is sampled in the middle of the
bit period. The receiver repeats this operation for each data bit, waiting one full bit time to
between sampling each data bit.
After the receiver has sampled the last data bit, it waits one full bit time and sample the
middle of the stop bit. If the stop bit is Low, the receiver detects a framing error.
Figure 63. Interfacing the serial pin with an RS-232 Interface (2)
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
RS232 TX
RS232 RX
ST
Figure
D0
Figure 64. OCD Serial Data Format
D1
RS-232
Tranceiver
64).
P R E L I M I N A R Y
D2
D3
Open-Drain
Buffer
D4
D5
Vdd
10 k
D6

DBG pin
D7
SP
Product Specification
ZNEO
On-Chip Debugger
Z16F Series
301