STM32F103C8T6TR STMicroelectronics, STM32F103C8T6TR Datasheet - Page 51

• Manufacturer Part Number: STM32F103C8T6TR
• Description: MCU ARM 64KB FLASH MEM 48-LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103C8T6TR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: 497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32497-8511 - KIT STARTER FOR STM32 512K FLASH497-6438 - BOARD EVALUTION FOR STM32 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

STM32F103xx
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
Refer to
alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 36.
1. TBD = to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Depends on f
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
t
t
t
t
t
t
dis(SO)
t
w(SCKH)
v(SO)
t
w(SCKL)
v(MO)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
h(NSS)
t
su(MI)
t
h(MO)
su(SI)
h(MI)
h(SO)
t
t
the data.
the data in Hi-Z
h(SI)
r(SCK)
f(SCK)
f
SCK
c(SCK)
(2)(4)
(2)(1)
(2)(1)
(2)
(2)(5)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Section 5.3.12: I/O port pin characteristics
(2)
SPI clock frequency
SPI clock rise and fall
time
NSS setup time
NSS hold time
SCK high and low
time
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time
Data output valid time
Data output hold time
SPI characteristics
PCLK
Table
Parameter
. For example, if f
7.
PCLK
(1)
Slave mode (after enable edge)
Slave mode (after enable edge)
= 8MHz, then t
Master mode, f
Master mode (after enable
Master mode (after enable
Master mode, f
Capacitive load: C=50 pF
Slave mode, f
Slave mode, f
PCLKx
Master mode
Master mode
Master mode
presc = TBD
Conditions
Slave mode
Slave mode
Slave mode
Slave mode
Slave mode
Slave mode
Slave mode
f
f
PCLK
PCLK
edge)
edge)
frequency and V
PCLK
= TBD
= TBD
PCLK
PCLK
PCLK
PCLK
for more details on the input/output
= 1/f
Table 36
= TBD
= TBD
= TBD,
= TBD
PLCLK
=125 ns and t
are derived from tests
DD
TBD
TBD
Electrical characteristics
TBD
TBD
supply voltage conditions
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
0
0
(3)
(3)
v(MO)
= 255 ns.
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MHz
Unit
51/67
ns