ST72F63BK4M1 STMicroelectronics, ST72F63BK4M1 Datasheet - Page 76

• Manufacturer Part Number: ST72F63BK4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-2115-5

On-chip peripherals
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Input Capture 1 High register (IC1HR)
Reset value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
Input Capture 1 Low register (IC1LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
Output Compare 1 High register (OC1HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
Output Compare 1 Low register (OC1LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
MSB
MSB
MSB
7
7
7
[1:0] Reserved, must be kept cleared.
3 OCF2 output Compare Flag 2.
2 TIMD Timer disable.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce
power consumption. Access to the timer registers is still available, allowing the
timer configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Doc ID 7516 Rev 8
Read/write
Read only
Read only
ST7263Bxx
LSB
LSB
LSB
0
0
0