ST72F63BK4M1 STMicroelectronics, ST72F63BK4M1 Datasheet - Page 160

• Manufacturer Part Number: ST72F63BK4M1
• Description: IC MCU 8BIT LS 16K 34-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK4M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• For Use With: 497-5521 - EVAL BOARD LOW SPEED USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-2115-5

Electrical characteristics
13.10.3
160/186
I
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDAI and SCLI).
The ST7 I
described in the following table.
Subject to general operating conditions for V
Table 76.
1. Data based on standard I
2. At 4 MHz f
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
Symbol
t
t
t
t
t
t
w(SCLH)
w(STO:S
w(SCLL)
t
su(SDA)
t
t
su(STO)
C interface
t
t
t
su(STA)
h(SDA)
r(SDA)
r(SCL)
f(SDA)
h(STA)
f(SCL)
approximately 260 KHz.
period of SCL signal.
undefined region of the falling edge of SCL.
TA)
C
b
2
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
Capacitive load for each bus line
C interface meets the requirements of the standard I
CPU
I
2
C characteristics
, max.I
2
C speed (400 kHz) is not achievable. In this case, max. I
Parameter
2
C protocol requirement, not tested in production.
Doc ID 7516 Rev 8
DD
, f
OSC
Standard mode
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
-
-
-
, and T
I
2
C
(1)
1000
Max
300
400
A
-
-
-
-
-
-
-
-
unless otherwise specified.
2
C communication protocol
Fast mode I
20+0.1C
20+0.1C
2
C speed will be
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
-
b
b
2
900
Max
C
300
300
400
ST7263Bxx
(1)(2)
-
-
-
-
-
-
-
(3)
Unit
pF
µs
ns
µs
µs
µs