LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 725
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.1.10 Software Single Request Register (DMACSoftSReq - 0xFFE0 4024)
6.1.12 Software Last Single Request Register (DMACSoftLSReq - 0xFFE0 402C)
6.1.11 Software Last Burst Request Register (DMACSoftLBreq - 0xFFE0 4028)
The DMACSoftSReq Register is read/write and enables DMA single requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates which
sources are requesting single DMA transfers. A request can be generated from either a
peripheral or the software request register.
DMACSoftSReq Register.
Table 662. Software Single Request register (DMACSoftSReq - address 0xFFE0 4024) bit
The DMACSoftLBReq Register is read/write and enables DMA last burst requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates which
sources are requesting last burst DMA transfers. A request can be generated from either
a peripheral or the software request register.
the DMACSoftLBReq Register.
Table 663. Software Last Burst Request register (DMACSoftLBReq - address 0xFFE0 4028)
The DMACSoftLSReq Register is read/write and enables DMA last single requests to be
generated by software. A DMA request can be generated for each source by writing a 1 to
the corresponding register bit. A register bit is cleared when the transaction has
completed. Writing 0 to this register has no effect. Reading the register indicates which
sources are requesting last single DMA transfers. A request can be generated from either
a peripheral or the software request register.
the DMACSoftLSReq Register.
Bit
0
1
2
3
4
31:5
Bit
3:0
4
31:5
Symbol
-
SoftLBReqSDMMC Software last burst request flags for SD/MMC.
-
Symbol
SoftReqSSP0Tx
SoftReqSSP0Rx
SoftReqSSP1Tx
SoftReqSSP1Rx
SoftReqSDMMC
-
description
bit description
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Single software request flag for SSP0 Tx.
Single software request flag for SSP0 Rx.
Single software request flag for SSP1 Tx.
Single software request flag for SSP1 Rx.
Single software request flag for SD/MMC.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Table 32–662
Table 32–663
Table 32–664
shows the bit assignments of the
shows the bit assignments of
shows the bit assignments of
UM10237
© NXP B.V. 2009. All rights reserved.
725 of 792
Reset
Value
0
0
0
0
0
NA
Reset
Value
NA
0
NA
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