LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 697
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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1. How to read this chapter
2. Features
3. Applications
4. Description
UM10237_4
User manual
Remark: This chapter describes the boot process for flashless parts LPC2420/60 and
LPC2470. It does not apply to parts LPC2458, LPC2468, and LPC2478.
The on-chip bootloader version 3.4 controls the boot process for flashless LPC2400 parts
LPC2420/60 and LPC2470.
The boot loader provides both In-System and In-Application programming interfaces for
programming the on-chip memory.
The bootloader is designed as a tool that enables the user to load system specific
application for further programming of in system available off-chip Flash and/or RAM
resources. The bootloader itself does not contain any external memory programming
algorithms. The bootloader implemented in LPC2460/70 supports a limited set of
commands dedicated to code download and its execution from on-chip RAM only. UART0
is the sole serial channel the boot loader can use for data download. Although a fractional
divider is available in the UART0, it is not used by the on-chip bootloader.
The boot loader code is executed every time the part is powered on or reset. The loader
can execute the ISP command handler or the user application code. A LOW level after
reset at the P2.10 pin is considered as an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2.10 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
•
•
UM10237
Chapter 31: LPC24XX On-chip bootloader for flashless parts
Rev. 04 — 26 August 2009
In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip memory, using the boot loader software and UART0 serial
port. This can be done when the part resides in the end-user board.
In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip memory, as directed by the end-user application
code.
Rev. 04 — 26 August 2009
© NXP B.V. 2009. All rights reserved.
User manual
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