LPC2460FET208,551 NXP Semiconductors, LPC2460FET208,551 Datasheet - Page 568
LPC2460FET208,551
Manufacturer Part Number
LPC2460FET208,551
Description
IC ARM7 MCU ROMLESS 208TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2460FET208,551
Program Memory Type
ROMless
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2460, MCB2460U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4260
935283232551
LPC2460FET208-S
935283232551
LPC2460FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2460FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
6.10 Data Counter Register (MCIDataCnt - 0xE008 C030)
6.9 Data Control Register (MCIDataCtrl - 0xE008 C02C)
The MCIDataCtrl register controls the DPSM.
the MCIDataCtrl register.
Table 501: Data Control register (MCIDataCtrl - address 0xE008 C02C) bit description
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
Data transfer starts if 1 is written to the enable bit. Depending on the direction bit, the
DPSM moves to the WAIT_S or WAIT_R state. It is not necessary to clear the enable bit
after the data transfer. BlockSize controls the data block length if Mode is 0, as shown in
Table
Table 502: Data Block Length
The MCIDataCnt register loads the value from the data length register (see
21–6.8 “Data Length Register (MCIDataLength - 0xE008
from the IDLE state to the WAIT_R or WAIT_S state. As data is transferred, the counter
decrements the value until it reaches 0. The DPSM then moves to the IDLE state and the
data status end flag is set.
register.
Bit
0
1
2
3
7:4
31:8 -
Block Size
0
1
...
11
12:15
21–502.
Symbol
Enable
Direction
Mode
DMAEnable
BlockSize
Value Description
0
1
0
1
0
1
Rev. 04 — 26 August 2009
Block Length
2
2
-
2
Reserved.
0
1
11
Data transfer enable.
Data transfer direction:
From controller to card.
From card to controller.
Data transfer mode:
Block data transfer.
Stream data transfer.
Enable DMA:
DMA disabled.
DMA enabled.
Data block length
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
= 1 byte.
Table 21–503
= 2 bytes.
= 2048 bytes.
Chapter 21: LPC24XX SD/MMC card interface
shows the bit assignment of the MCIDataCnt
Table 21–501
C028)”) when the DPSM moves
shows the bit assignment of
UM10237
© NXP B.V. 2009. All rights reserved.
Section
568 of 792
0
0
0
0
0
Reset
Value
NA
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