DSPIC30F4011-20I/ML Microchip Technology, DSPIC30F4011-20I/ML Datasheet - Page 81

• Manufacturer Part Number: DSPIC30F4011-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401120/ML

12.2.2
CPU Idle mode allows input capture module operation
with full functionality. In the CPU Idle mode, the interrupt
mode selected by the ICI<1:0> bits are applicable, as
well as the 4:1 and 16:1 capture prescale settings which
are defined by control bits ICM<2:0>. This mode
requires the selected timer to be enabled. Moreover, the
ICSIDL bit must be asserted to a logic ‘0’.
If
ICM<2:0> = 111 in CPU Idle mode, the input capture
pin will serve only as an external interrupt pin.
© 2007 Microchip Technology Inc.
the
input
INPUT CAPTURE IN CPU IDLE
MODE
capture
module
is
defined
as
12.3
The input capture channels have the ability to generate
an interrupt, based upon the selected number of
capture events. The selection number is set by control
bits, ICI<1:0> (ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx register.
Enabling an interrupt is accomplished via the respec-
tive Capture Channel Interrupt Enable (ICxIE) bit. The
capture interrupt enable bit is located in the
corresponding IECx register.
dsPIC30F4011/4012
Input Capture Interrupts
DS70135E-page 79