DSPIC30F4011-20I/ML Microchip Technology, DSPIC30F4011-20I/ML Datasheet - Page 160

• Manufacturer Part Number: DSPIC30F4011-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401120/ML

TABLE 21-7:
Note:
TABLE 21-8:
Note:
RCON
OSCCON 0742
FOSC
FWDT
FBORPOR
FGS
Name
File Name
SFR
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Addr. Bit 15
0740 TRAPR IOPUWR BGST
F80000
F80002
F80004
F8000A
Addr.
TUN3
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
Bit 14
TUN2
Bits 23-16
—
—
—
—
Bit 13
COSC<1:0>
FWDTEN
MCLREN
Bit 15
Bit 12
FCKSM<1:0>
—
—
Bit 11
TUN1
Bit 14
—
—
—
Bit 10
TUN0
Bit 13
—
—
—
—
Bit 9
NOSC<1:0>
Bit 12
—
—
—
—
Bit 8
Bit 11
—
—
—
—
EXTR
Bit 7
POST<1:0>
PWMPIN
Bit 10
—
—
—
SWR
Bit 6
SWDTEN
HPOL
Bit 9
LOCK
—
—
Bit 5
FOS<1:0>
LPOL
Bit 8
—
—
WDTO
Bit 4
—
BOREN
Bit 7
SLEEP
—
—
—
Bit 3
CF
Bit 6
—
—
—
—
IDLE
Bit 2
—
Bit 5
FWPSA<1:0>
LPOSCEN OSWEN Depends on Configuration bits.
—
BORV<1:0>
—
Bit 1
BOR
Bit 4
—
—
Bit 0
POR
Bit 3
—
—
Depends on type of Reset.
Bit 2
—
—
FWPSB<3:0>
FPR<3:0>
Reset State
Bit 1
GCP
FPWRT<1:0>
GWRP
Bit 0