DSPIC30F4011-20I/ML Microchip Technology, DSPIC30F4011-20I/ML Datasheet - Page 229

• Manufacturer Part Number: DSPIC30F4011-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4011-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401120/ML

Timing Specifications
Trap Vectors ....................................................................... 42
Traps ................................................................................... 41
U
UART
© 2007 Microchip Technology Inc.
SPI Master Mode (CKE = 0) ..................................... 196
SPI Master Mode (CKE = 1) ..................................... 197
SPI Slave Mode (CKE = 0) ....................................... 199
SPI Slave Mode (CKE = 1) ....................................... 201
Timer1 External Clock............................................... 187
Timer2 and Timer4 External Clock ........................... 188
Timer3 and Timer5 External Clock ........................... 188
PLL Clock.................................................................. 181
PLL Jitter................................................................... 181
Hard and Soft.............................................................. 42
Trap Sources .............................................................. 41
Address Detect Mode ............................................... 119
Alternate I/O.............................................................. 117
Auto-Baud Support ................................................... 120
Baud Rate Generator................................................ 119
Disabling ................................................................... 117
Enabling and Setting Up ........................................... 117
Loopback Mode ........................................................ 119
Module Overview ...................................................... 115
Operation During CPU Sleep and Idle Modes .......... 120
Receiving Data.......................................................... 118
Reception Error Handling.......................................... 118
In 8-bit or 9-bit Data Mode ................................ 118
Interrupt ............................................................ 118
Receive Buffer (UxRCB) ................................... 118
Framing Error (FERR) ...................................... 119
Idle Status ......................................................... 119
Parity Error (PERR) .......................................... 119
Receive Break .................................................. 119
Receive Buffer Overrun Error (OERR Bit) ........ 118
Unit ID Locations .............................................................. 145
Universal Asynchronous Receiver
W
Wake-up from Sleep ......................................................... 145
Wake-up from Sleep and Idle ............................................. 43
Watchdog Timer (WDT)............................................ 145, 155
WWW Address ................................................................. 228
WWW, On-Line Support ....................................................... 6
dsPIC30F4011/4012
Setting Up Data, Parity and Stop Bit
Transmitting Data ..................................................... 117
UART1 Register Map ............................................... 121
UART2 Register Map ............................................... 121
Transmitter Module (UART) ..................................... 115
Enabling and Disabling............................................. 155
Operation.................................................................. 155
Selections ......................................................... 117
Break ................................................................ 118
In 8-bit Data Mode ............................................ 117
In 9-bit Data Mode ............................................ 117
Interrupt ............................................................ 118
Transmit Buffer (UxTXB) .................................. 117
DS70135E-page 227