AT32UC3A0128-ALUR Atmel, AT32UC3A0128-ALUR Datasheet - Page 95
![MCU AVR32 128K FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0128-ALUR
Manufacturer Part Number
AT32UC3A0128-ALUR
Description
MCU AVR32 128K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0128-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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15.5
32058J–AVR32–04/11
Functional Description
The WDT is enabled by writing the EN bit in the CTRL register to one. This also enables the RC
clock for the prescaler. The PSEL bitfield in the same register selects the watchdog timeout
period:
The next timeout period will begin as soon as the watchdog reset has occured and count down
during the reset sequence. Care must be taken when selecting the PSEL value so that the time-
out period is greater than the startup time of the chip, otherwise a watchdog reset can reset the
chip before any code has been run.
To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with
the KEY field set to 0x55, then 0xAA without changing the other bitfields. Failure to do so will
cause the write operation to be ignored, and CTRL does not change value.
The CLR register must be written with any value with regular intervals shorter than the watchdog
timeout period. Otherwise, the device will receive a soft reset, and the code will start executing
from the boot vector.
When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mode, leaving the WDT operational.
T
WDT
= 2
(PSEL+1)
/ f
RC
AT32UC3A
95
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