AT32UC3A0128-ALUR Atmel, AT32UC3A0128-ALUR Datasheet - Page 279

• Manufacturer Part Number: AT32UC3A0128-ALUR
• Description: MCU AVR32 128K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 69
• Interface Type: Ethernet/I2S/JTAG/SPI/TWI/USART
• Number Of Timers: 3
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• CKG: Receive Clock Gating Selection
• CKI: Receive Clock Inversion
0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal out-
put is shifted out on Receive Clock rising edge.
1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-
put is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
• CKO: Receive Clock Output Mode Selection
• CKS: Receive Clock Selection
32058J-AVR32-04/11
0x3-0x7
CKO
CKG
0x0
0x1
0x2
CKS
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Receive Clock Output Mode
None
Continuous Receive Clock
Receive Clock only during data transfers
Reserved
None, continuous clock
Receive Clock enabled only if RX_FRAME_SYNC Low
Receive Clock enabled only if RX_FRAME_SYNC High
Reserved
Selected Receive Clock
Divided Clock
TX_CLOCK Clock signal
RX_CLOCK pin
Reserved
Receive Clock Gating
AT32UC3A
RX_CLOCK pin
Input-only
Output
Output
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