AT32UC3A0128-ALUR Atmel, AT32UC3A0128-ALUR Datasheet - Page 754

• Manufacturer Part Number: AT32UC3A0128-ALUR
• Description: MCU AVR32 128K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 69
• Interface Type: Ethernet/I2S/JTAG/SPI/TWI/USART
• Number Of Timers: 3
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

36.9.5
32058J–AVR32–04/11
MEMORY_WORD_ACCESS
Table 36-7.
Starting in Run-Test/Idle, SAB data are accessed in the following way:
For any operation, the full 36 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 36-8.
This instruction allows access to the entire Service Access Bus data area. Data are accessed
through a 34-bit word index, a direction bit, and 32 bits of data. This instruction is identical to
MEMORY_SIZED_ACCESS except that it always does word sized accesses. The size field is
implied, and the two lowest address bits are removed.
Size field value
01
10
11
Instructions
IR input value
IR output value
DR Size
DR input value (Address phase)
DR input value (Data read phase)
DR input value (Data write phase)
DR output value (Address phase)
DR output value (Data read phase)
DR output value (Data write phase)
1. Select the DR Scan path.
2. Scan in the 36-bit address of the data to access, a 2-bit access size, and a direction bit
3. Go to Update-DR and re-enter Select-DR Scan.
4. For a read operation, scan out the contents of the addressed area. For a write opera-
5. Return to Run-Test/Idle.
(1=read, 0=write).
tion, scan in the new contents of the area.
Size Field Semantics
MEMORY_SIZED_ACCESS details
Access size
Halfword (16 bits)
Word (32 bits)
Reserved
Details
10101 (0x15)
peb01
39 bits
aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx
dddddddd dddddddd dddddddd dddddddd xxxxxxx
xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
xxxxxeb dddddddd dddddddd dddddddd dddddddd
xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Data alignment
Address modulo 4 : data alignment
0: dddddddd dddddddd xxxxxxxx xxxxxxxx
1: Not allowed
2: xxxxxxxx xxxxxxxx dddddddd dddddddd
3: Not allowed
Address modulo 4 : data alignment
0: dddddddd dddddddd dddddddd dddddddd
1: Not allowed
2: Not allowed
3: Not allowed
N/A
AT32UC3A
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