AT32UC3A0128-ALUR Atmel, AT32UC3A0128-ALUR Datasheet - Page 519

• Manufacturer Part Number: AT32UC3A0128-ALUR
• Description: MCU AVR32 128K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 69
• Interface Type: Ethernet/I2S/JTAG/SPI/TWI/USART
• Number Of Timers: 3
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 30-20. Example of an OUT Endpoint with 1 Data Bank
Figure 30-21. Example of an OUT Endpoint with 2 Data Banks
30.7.2.13.2 Detailed Description
30.7.2.14
32058J–AVR32–04/11
RXOUTI
FIFOCON
RXOUTI
FIFOCON
OUT
OUT
Underflow
(bank 0)
DATA
(bank 0)
DATA
The data is read by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be read by the firmware while the follow-
ing one is being written by the host. Then, when the firmware clears FIFOCON, the following
bank may already be ready and RXOUTI is set immediately.
This error exists only for isochronous IN/OUT endpoints. It raises the Underflow interrupt
(UNDERFI), what triggers an EPXINT interrupt if UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USB controller.
•when the bank is full, RXOUTI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing RXOUTI;
•the firmware can read the byte count of the current bank from BYCT to know how many bytes
•the firmware reads the data from the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware frees the bank and switches to the next bank (if any) by clearing FIFOCON.
RXOUTE = 1;
to read, rather than polling RWALL;
Data register (USB_FIFOX_DATA), until all the expected data frame is read or the bank is
empty (in which case RWALL is cleared by hardware and BYCT reaches 0);
HW
ACK
HW
ACK
SW
read data from CPU
SW
BANK 0
NAK
OUT
read data from CPU
BANK 0
(bank 1)
DATA
SW
OUT
ACK
(bank 0)
DATA
HW
SW
HW
ACK
read data from CPU
SW
read data from CPU
AT32UC3A
BANK 1
SW
BANK 0
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