ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 296

• Manufacturer Part Number: ATMEGA32U4-MUR
• Description: MCU AVR 16K FLASH 16MHZ 44VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U4-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7766F–AVR–11/10
in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See
297
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see
Figure 24-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 24-5. ADC Timing Diagram, Single Conversion
for details on differential conversion timing.
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
1
2
2
MUX and REFS
Update
MUX and REFS
Update
3
Sample & Hold
12
4
13
5
14
6
7
15
One Conversion
Sample & Hold
16
8
First Conversion
9
17
10
18
Conversion
Complete
19
11
12
20
“Differential Channels” on page
13
21
ATmega16/32U4
22
Sign and MSB of Result
Conversion
Complete
LSB of Result
Next Conversion
1
23
2
24
MUX and REFS
Update
Table
3
25
24-1.
Sign and MSB of Result
Next
Conversion
1
LSB of Result
2
and REFS
Update
MUX
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3