ATTINY13A-SU Atmel, ATTINY13A-SU Datasheet

IC MCU AVR 1K FLASH 20MHZ 8SOIC

ATTINY13A-SU

Manufacturer Part Number
ATTINY13A-SU
Description
IC MCU AVR 1K FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY13A-SU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI
Total Internal Ram Size
64Byte
# I/os (max)
6
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
On-chip Adc
4-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC EIAJ
Processor Series
ATTINY1x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
Minimum Operating Temperature
- 40 C
Package
8SOIC EIAJ
Family Name
ATtiny
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Compliant

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Features
High Performance, Low Power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Speed Grade:
Industrial Temperature Range
Low Power Consumption
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
– 64 Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 Years at 85°C/100 Years at 25°C (see
– Programming Lock for Self-Programming Flash & EEPROM Data Security
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit with Software Disable Function
– Internal Calibrated Oscillator
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 10-pad MLF: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
– 1.8 – 5.5V
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 10 MHz @ 2.7 – 5.5V
– 0 – 20 MHz @ 4.5 – 5.5V
– Active Mode:
– Idle Mode:
• 190 µA at 1.8 V and 1 MHz
• 24 µA at 1.8 V and 1 MHz
®
8-Bit Microcontroller
page
6)
8-bit
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
ATtiny13A
Rev. 8126E–AVR–07/10

Related parts for ATTINY13A-SU

ATTINY13A-SU Summary of contents

Page 1

... Industrial Temperature Range • Low Power Consumption – Active Mode: • 190 µA at 1.8 V and 1 MHz – Idle Mode: • 24 µA at 1.8 V and 1 MHz ® 8-Bit Microcontroller page 6) 8-bit Microcontroller with 1K Bytes In-System Programmable Flash ATtiny13A Rev. 8126E–AVR–07/10 ...

Page 2

... Pin Configurations Figure 1-1. Pinout of ATtiny13A (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect ...

Page 3

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13A as listed on 55. 1.1.4 RESET Reset input ...

Page 4

... Overview The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 5

... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The ATtiny13A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. 8126E–AVR–07/10 ...

Page 6

... C is compiler dependent. Please confirm with the C compiler documen- tation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATtiny13A 6 8126E–AVR–07/10 ...

Page 7

CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...

Page 8

... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny13A 8 8126E–AVR–07/10 ...

Page 9

SREG – Status Register Bit 0x3F Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then ...

Page 10

... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATtiny13A 10 shows the structure of the 32 general purpose working registers in the CPU. ...

Page 11

Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing ...

Page 12

... The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the ATtiny13A 12 , directly generated from the selected clock source for the ...

Page 13

RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic ...

Page 14

... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny13A 14 ; set Global Interrupt Enable See “ ...

Page 15

... Since all AVR instructions are bits wide, the Flash is organized as 512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13A Pro- gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations. “Memory Programming” on page 103 loading using the SPI pins ...

Page 16

... EEPROM Data Memory The ATtiny13A contains 64 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

Page 17

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...

Page 18

... Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: ATtiny13A 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; See “Code Examples” on page 6. “OSCCAL – Oscillator Calibration Register” on ...

Page 19

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

Page 20

... I/O Memory The I/O space definition of the ATtiny13A is shown in All ATtiny13A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

Page 21

... Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny13A. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny13A and will always read as zero. • ...

Page 22

... When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read opera- tion write operation is in progress neither possible to read the EEPROM, nor to change the EEARL Register. ATtiny13A 22 8126E–AVR–07/10 ...

Page 23

System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 24

... Table 6-2. 6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown run the device on an external clock, the CKSEL fuses must be programmed to “00”. Figure 6-2. ATtiny13A 24 Device Clocking Options Select page 24) page 26) 1. For all fuses “1” means unprogrammed while “0” means programmed. ...

Page 25

When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-3. Table 6-3. SUT[1: When applying an external clock required to avoid sudden changes in the ...

Page 26

... In-System or High-voltage Programmer. 6.3 System Clock Prescaler The ATtiny13A system clock can be divided by setting the on page processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk ...

Page 27

... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in ATtiny13A and it will always read zero. • Bits 6:0 – CAL[6:0]: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari- ations from the Oscillator frequency ...

Page 28

... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...

Page 29

Table 6-8. CLKPS3 8126E–AVR–07/10 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 ...

Page 30

... Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator ATtiny13A 30 presents the different clock systems in the ATtiny13A, and their distribu- Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains X ...

Page 31

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM[1:0] bits are written to ...

Page 32

... If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to ATtiny13A 32 for examples. “Analog Comparator” on page 79 “ ...

Page 33

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock ...

Page 34

... Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot be used when the ADC is shut down. ATtiny13A 34 Sleep Mode Select SM0 ...

Page 35

System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...

Page 36

... Reset Sources The ATtiny13A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. ...

Page 37

... Figure 8-4. 8.2.3 Brown-out Detection ATtiny13A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

Page 38

... Watchdog Timer ATtiny13A has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system ...

Page 39

If the system doesn't restart the counter, an interrupt or system reset will be issued. Figure 8-7. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the ...

Page 40

... If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condi- tion, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situa- ATtiny13A 40 r16, MCUSR r16, (0xff - (1< ...

Page 41

Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C ...

Page 42

... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

Page 43

This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Inter- rupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not be done within the interrupt service routine ...

Page 44

... Table 8-2. WDP3 ATtiny13A 44 Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator WDP2 WDP1 WDP0 Typical Time-out at Cycles V = 5.0V CC Reserved 8126E–AVR–07/10 ...

Page 45

... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13A. For a general explanation of the AVR interrupt handling, refer to page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny13A are described in Table 9-1. Vector No. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...

Page 46

... SLEEP command. 9.2.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 9-1. ATtiny13A 46 “Clock Systems and their Distribution” on page 23. Timing of pin change interrupts pin_lat ...

Page 47

... Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...

Page 48

... Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one) ...

Page 49

I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...

Page 50

... PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. ATtiny13A 50 (1) SLEEP ...

Page 51

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured ...

Page 52

... In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK INSTRUCTIONS SYNC LATCH ATtiny13A 52 XXX PINxn r17 Figure 10-4 on page 52. The out instruction sets the “SYNC LATCH” signal at the ...

Page 53

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with a pull-up assigned to port pin 4. The resulting ...

Page 54

... Most port pins have alternate functions in addition to being general digital I/Os. shows how port pin control signals from the simplified by alternate functions. Figure 10-5. Alternate Port Functions Note: ATtiny13A 54 or GND is not recommended, since this may cause excessive currents if the pin is CC PUOExn ...

Page 55

The overriding signals may not be present in all port pins, but description applicable to all port pins in the AVR microcontroller family. Table 10-2 on page 55 indexes from signals are generated internally in the modules having the alternate ...

Page 56

... Table 10-4. Signal PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: ATtiny13A 56 Port B Pins Alternate Functions Port Pin Alternate Function RESET: Reset Pin dW: debugWIRE I/O PB5 ADC0: ADC Input Channel 0 PCINT5: Pin Change Interrupt, Source 5 ADC2: ADC Input Channel 2 ...

Page 57

... Initial Value • Bits 7, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See figuring the Pin” ...

Page 58

... PINB – Port B Input Pins Address Bit 0x16 Read/Write Initial Value ATtiny13A – – PINB5 PINB4 R R R/W R N/A N PINB3 PINB2 PINB1 PINB0 R/W R/W R/W R/W N/A N/A N/A N/A 8126E–AVR–07/10 PINB ...

Page 59

... Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 11-1. 8-bit Timer/Counter Block Diagram 8126E–AVR–07/10 “Pinout of ATtiny13A” on page “Register Description” on page Count Clear Control Logic ...

Page 60

... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 11-2 shows a block diagram of the counter and its surroundings. ATtiny13A 60 See “Output Compare Unit” on page 61. Table 11-1 on page 60 are also used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00 ...

Page 61

Figure 11-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...

Page 62

... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform ATtiny13A 62 DATA BUS OCRnx ...

Page 63

Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...

Page 64

... OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. ATtiny13A 64 See “Register Description” on page 70. ...

Page 65

The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. Figure 11-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt ...

Page 66

... The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result ATtiny13A 66 Figure 11-6 on page 66 ...

Page 67

COM0A[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle ...

Page 68

... The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. The figure shows the count sequence close to the MAX value in all modes other than phase cor- rect PWM mode. ATtiny13A 68 Table 11-4 on page f OCnxPCPWM ...

Page 69

Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOVn Figure 11-9 Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 11-10 mode and PWM ...

Page 70

... When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[2:0] bit setting. Table 11-2 or CTC mode (non-PWM). Table 11-2. COM0A1 ATtiny13A 70 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O TOP - 1 TOP 7 6 ...

Page 71

Table 11-3 PWM mode. Table 11-3. COM0A1 Note: Table 11-4 correct PWM mode. Table 11-4. COM0A1 Note: • Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode These bits control the Output ...

Page 72

... PWM mode. Table 11-7. COM0B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. ATtiny13A 72 Compare Output Mode, non-PWM Mode COM0B0 Description 0 Normal port operation, OC0B disconnected. 1 Toggle OC0B on Compare Match ...

Page 73

Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...

Page 74

... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...

Page 75

... Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...

Page 76

... Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...

Page 77

Timer/Counter Prescaler 12.1 Overview The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency ( ...

Page 78

... Timer/Counter start counting. • Bit 0 – PSR10: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ATtiny13A 78 Clear Synchronization 1. The synchronization logic on the input pins ( ...

Page 79

Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...

Page 80

... When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13A and will always read as zero. ATtiny13A 80 ...

Page 81

Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 13-2. ACIS1 When changing the ACIS1/ACIS0 bits, ...

Page 82

... ADC Start Conversion by Auto Triggering on Interrupt Sources • Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler 14.2 Overview The ATtiny13A features a 10-bit successive approximation ADC. A block diagram of the ADC is shown in Figure 14-1. Analog to Digital Converter Block Schematic V CC ADC3 ADC2 ...

Page 83

The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures ...

Page 84

... ADC can be higher than 200 kHz to get a higher sample rate. Figure 14-3. ADC Prescaler The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. ATtiny13A 84 ADTS[2:0] ADIF SOURCE 1 ...

Page 85

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. ...

Page 86

... ADIF ADCH ADCL In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. Figure 14-7. ADC Timing Diagram, Free Running Conversion ATtiny13A 86 below. This assures a fixed delay from the trigger event to the start of conversion ...

Page 87

For a summary of conversion times, see Table 14-1. Condition First conversion Normal conversions Auto Triggered conversions 14.6 Changing Channel or Reference Selection The MUXn and REFS[1:0] bits in the ADMUX Register are single buffered through a temporary register to ...

Page 88

... ADC, or not. When the channel is selected, the source drives the S/H capacitor through the series resistance (combined resistance in input path). Figure 14-8. Analog Input Circuitry Note: ATtiny13A 88 ) indicates the conversion range for the ADC. Single REF will result in codes close to 0x3FF ...

Page 89

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible source with higher imped- ance is used, the sampling ...

Page 90

... Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 14-10. Gain Error Output Code ATtiny13A 90 Offset Error Ideal ADC Actual ADC ...

Page 91

Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 14-11. Integral Non-linearity (INL) Output Code ...

Page 92

... Read/Write Initial Value • Bits 7, 4:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bit 6 – REFS0: Reference Selection Bit This bit selects the voltage reference for the ADC, as shown in during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set) ...

Page 93

Bits 1:0 – MUX[1:0]: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 14-3 in effect until this conversion is complete (ADIF in ADCSRA is set). ...

Page 94

... When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. ATtiny13A 94 ADC Prescaler Selections ADPS1 ...

Page 95

... Initial Value • Bits 7, 5:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and will always read as zero. • Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion ...

Page 96

... Figure 15-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL fuses. Figure 15-1. The debugWIRE Setup ATtiny13A 96 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator dW dW(RESET) GND 1 ...

Page 97

When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the ...

Page 98

... Page Write operation or by writing the CTPB bit in SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. ATtiny13A 98 The CPU is halted during the Page Erase operation. ...

Page 99

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 16.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR ...

Page 100

... To read the Fuse Low Byte (FLB), follow the below procedure: 1. Load the Z-pointer with 0x0000. 2. Set RFLB and SELFPRGEN bits in SPMCSR. 3. Issuing an LPM instruction within three clock cycles will FLB in the destination register. If successful, the contents of the destination register are as follows. Bit Rd ATtiny13A 100 – ...

Page 101

To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd See sections for more information on ...

Page 102

... Initial Value • Bits 7:5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13A and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. • ...

Page 103

... This section describes how ATtiny13A memories can be programmed. 17.1 Program And Data Memory Lock Bits ATtiny13A provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in erased to “1” with the Chip Erase command, only. ...

Page 104

... Fuse Bytes The ATtiny13A has two fuse bytes. describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 17-3. Fuse Bit – ...

Page 105

... Calibration Bytes The signature area of the ATtiny13A contains two bytes of calibration data for the internal oscil- lator. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 9.6 MHz operation. During reset, this byte is automatically written into the OSCCAL register to ensure correct frequency of the oscillator ...

Page 106

... Program and EEPROM arrays into 0xFF. Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f High: > 2 CPU clock cycles for f ATtiny13A 106 Figure 17-1. PB5 ...

Page 107

... Serial Programming Algorithm When writing serial data to the ATtiny13A, data is clocked on the rising edge of SCK. When reading data from the ATtiny13A, data is clocked on the falling edge of SCK. See 18-4 on page 122 To program and verify the ATtiny13A in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...

Page 108

... Page (page access) Write EEPROM Memory 1100 0010 Page (page access) Read Lock Bits 0101 1000 Write Lock Bits 1010 1100 ATtiny13A 108 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Table 17-9. Instruction Format Byte 2 Byte 3 Byte4 ...

Page 109

... Low byte High Byte data out data in don’t care 17.7 High-Voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, lock bits and fuse bits in the ATtiny13A. Figure 17-2. High-voltage Serial Programming 8126E–AVR–07/10 Instruction Format ...

Page 110

... SII SDO 17.7.1 High-Voltage Serial Programming Algorithm To program and verify the ATtiny13A in the High-voltage Serial Programming mode, the follow- ing sequence is recommended (See instruction formats in The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that Vcc reaches at least 1.8V within the next 20 µ ...

Page 111

... Exit Programming mode by power the device down or by bringing RESET pin to 0V. Table 17-12. High-voltage Reset Characteristics Supply Voltage V CC 4.5V 5.5V 17.7.2 High-Voltage Serial Programming Instruction set The instruction set is described in Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx ...

Page 112

... Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A (Continued) Instruction Instr.1/5 SDI 0_00bb_bbbb_00 Load EEPROM SII 0_0000_1100_00 Page Buffer SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Program SII 0_0110_0100_00 EEPROM Page SDO x_xxxx_xxxx_xx SDI 0_00bb_bbbb_00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Write EEPROM Byte SDI ...

Page 113

... Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13A (Continued) Instruction Instr.1/5 SDI 0_0000_1000_00 Read Signature SII 0_0100_1100_00 Bytes SDO x_xxxx_xxxx_xx SDI 0_0000_1000_00 Read SII 0_0100_1100_00 Calibration Byte SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Load “No Operation” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx ...

Page 114

... Programming” cycle to finish. 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny13A, data is clocked on the rising edge of the serial clock, see 123 for details. ...

Page 115

Figure 17-4. High-voltage Serial Programming Waveforms SDI PB0 SII PB1 SDO PB2 SCI PB3 17.8.3 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data is latched into a page buffer. This allows one page of data ...

Page 116

... Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in page 111. 17.8.8 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V ATtiny13A 116 power off. CC Table 17-13 on 8126E–AVR–07/10 ...

Page 117

Electrical Characteristics 18.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...

Page 118

... I/O drive. 8. BOD Disabled. 18.3 Speed The maximum operating frequency of the device depends on supply voltage, V Figure 18-1, the relationship between maximum frequency and V to 4.5V. Figure 18-1. Maximum Frequency vs. V ATtiny13A 118 = -40°C to +85°C (Continued) A Condition f = 1MHz 4MHz, V ...

Page 119

Clock Characteristics 18.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics ...

Page 120

... Table 18-5. Symbol V POR V POA SR ON Note: 18.5.2 Brown-Out Detection Table 18-6. BODLEVEL[1:0] Fuses Note: ATtiny13A 120 Reset, Brown-out, and Internal Voltage Characteristics Parameter RESET Pin Threshold Voltage Minimum pulse width on (1) RESET Pin Brown-out Detector (2) Hysteresis Min Pulse Width on (2) ...

Page 121

Analog Comparator Characteristics Table 18-7. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage AIO I Input Leakage Current LAC Analog Propagation Delay (from saturation to slight overdrive) t APD Analog Propagation Delay (large step change) t Digital ...

Page 122

... Table 18-9. Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH t SHOX Note: ATtiny13A 122 MOSI t OVSH SCK t SHSL MISO MSB (MOSI) MSB (MISO) (SCK) SAMPLE Serial Programming Characteristics, T Parameter Oscillator Frequency V Oscillator Period Oscillator Frequency V Oscillator Period ...

Page 123

High-voltage Serial Programming Characteristics Figure 18-5. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) Table 18-10. High-voltage Serial Programming Characteristics Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB 8126E–AVR–07/10 t IVSH SCI (PB3) SDO ...

Page 124

... Example Estimate current consumption in idle mode, with Timer/Counter0 and ADC enabled, the device running at 2V and with 1MHz external clock. From Figure 19-7 on page 128 page 133 Timer/Counter0 supply current I therefore I ATtiny13A 124 × × operating voltage load capacitance and f ...

Page 125

Current Consumption in Active Mode Figure 19-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 19-2. Active Supply Current vs. Frequency ( MHz) 8126E–AVR–07/10 ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 1 0.9 0.8 0.7 ...

Page 126

... Figure 19-3. Active Supply Current vs. V Figure 19-4. Active Supply Current vs. V ATtiny13A 126 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 9.6 MHz 1 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4.8 MHz 3.5 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 (Internal RC Oscillator, 9.6 MHz ...

Page 127

Figure 19-5. Active Supply Current vs. V Figure 19-6. Active Supply Current vs. V 0.03 0.025 0.02 0.015 0.01 0.005 8126E–AVR–07/10 ACTIVE SUPPLY CURRENT vs. V INTERNAL WD OSCILLATOR, 128 KHz 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 ...

Page 128

... Current Consumption in Idle Mode Figure 19-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0.1 0.08 0.06 0.04 0.02 Figure 19-8. Idle Supply Current vs. Frequency ( MHz) ATtiny13A 128 IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0 0 0.1 0.2 0.3 0.4 Frequency (MHz) IDLE SUPPLY CURRENT vs ...

Page 129

Figure 19-9. Idle Supply Current vs. V Figure 19-10. Idle Supply Current vs. V 8126E–AVR–07/10 CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 9.6 MHz 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1 ...

Page 130

... Figure 19-11. Idle Supply Current vs. V 0.025 0.02 0.015 0.01 0.005 Figure 19-12. Idle Supply Current vs. V 0.006 0.005 0.004 0.003 0.002 0.001 ATtiny13A 130 (Internal RC Oscillator, 128 kHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL WD OSCILLATOR, 128 KHz 0 1.5 2 2.5 3 (32 kHz External Clock) CC IDLE SUPPLY CURRENT vs ...

Page 131

Current Consumption in Power-down Mode Figure 19-13. Power-down Supply Current vs. V Figure 19-14. Power-down Supply Current vs. V 8126E–AVR–07/10 POWER-DOWN SUPPLY CURRENT vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 ...

Page 132

... Current Consumption in Reset Figure 19-15. Reset Supply Current vs. V 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 Figure 19-16. Reset Supply Current vs. V ATtiny13A 132 CC Reset Pull-up) RESET SUPPLY CURRENT vs. V EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 0 0.1 0.2 0.3 ...

Page 133

Current Consumption of Peripheral Units Figure 19-17. Brownout Detector Current vs. V Figure 19-18. ADC Current vs. V 400 350 300 250 200 150 100 8126E–AVR–07/10 BROWNOUT DETECTOR CURRENT vs 1.5 ...

Page 134

... Figure 19-19. Analog Comparator Current vs. V 100 Figure 19-20. Programming Current vs. V 9000 8000 7000 6000 5000 4000 3000 2000 1000 ATtiny13A 134 ANALOG COMPARATOR CURRENT vs. V 1 PROGRAMMING CURRENT vs 1 1.0 MHz 3 3 °C 25 °C -40 ° ...

Page 135

Pull-up Resistors Figure 19-21. Pull-up Resistor Current vs. Input Voltage (I/O Pin, V Figure 19-22. Pull-up Resistor Current vs. Input Voltage (I/O Pin, V 8126E–AVR–07/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

Page 136

... Figure 19-23. Pull-up Resistor Current vs. Input Voltage (I/O Pin, V Figure 19-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V ATtiny13A 136 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 160 85 °C 25 °C 140 -40 °C 120 100 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE ...

Page 137

Figure 19-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V Figure 19-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 8126E–AVR–07/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE ...

Page 138

... Output Driver Strength (Low Power Pins) Figure 19-27. V Figure 19-28. V ATtiny13A 138 : I/O Pin Output Voltage vs. Source Current (Low Power Pins I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 0 I/O Pin Output Voltage vs. Source Current (Low Power Pins I/O PIN OUTPUT VOLTAGE vs ...

Page 139

Figure 19-29. V Figure 19-30. V 8126E–AVR–07/10 : I/O Pin Output Voltage vs. Source Current (Low Power Pins I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT LOW POWER PINS, V 5.2 5 4.8 4.6 4.4 4 ...

Page 140

... Figure 19-31. V Figure 19-32. V ATtiny13A 140 : I/O Pin Output Voltage vs. Sink Current (Low Power Pins I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT LOW POWER PINS, V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 I/O Pin Output Voltage vs. Sink Current (Low Power Pins I/O PIN OUTPUT VOLTAGE vs ...

Page 141

Output Driver Strength (Regular Pins) Figure 19-33. V Figure 19-34. V 8126E–AVR–07/10 : I/O Pin Output Voltage vs. Source Current (V OH I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 ...

Page 142

... Figure 19-35. V Figure 19-36. V ATtiny13A 142 : I/O Pin Output Voltage vs. Source Current (V OH I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 5.2 5 4.8 4.6 4.4 4 I/O Pin Output Voltage vs. Sink Current (V OL I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0.5 0.45 0.4 0.35 0.3 ...

Page 143

Figure 19-37. V Figure 19-38. V 8126E–AVR–07/10 : I/O Pin Output Voltage vs. Sink Current (V OL I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0. ...

Page 144

... Figure 19-39. V Figure 19-40. V ATtiny13A 144 : Reset Pin as I/O, Output Voltage vs. Source Current (V OH RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 1,6 1,4 1,2 1 0,8 0,6 0,4 0 0,1 0,2 0,3 0,4 : Reset Pin as I/O, Output Voltage vs. Source Current (V OH RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT ...

Page 145

Figure 19-41. V Figure 19-42. V 8126E–AVR–07/10 : Reset Pin as I/O, Output Voltage vs. Source Current (V OH RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 4,5 4 3,5 3 2,5 2 1 0,1 ...

Page 146

... Figure 19-43. V Figure 19-44. V ATtiny13A 146 : Reset Pin as I/O, Output Voltage vs. Sink Current (V OL RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 1,6 1,4 1,2 1 0,8 0,6 0 Reset Pin as I/O, Output Voltage vs. Sink Current (V OL RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT ...

Page 147

Input Thresholds and Hysteresis (for I/O Ports) Figure 19-45. V Figure 19-46. V 8126E–AVR–07/10 : Input Threshold Voltage vs I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC 3.5 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 ...

Page 148

... Figure 19-47. V Figure 19-48. V ATtiny13A 148 -V : Input Hysteresis vs I/O PIN INPUT HYSTERESIS vs. V 0.6 -40 °C 0.5 25 °C 0.4 85 °C 0.3 0.2 0.1 0 1 Input Threshold Voltage vs RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC V 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 (I/O Pin ...

Page 149

Figure 19-49. V Figure 19-50. V 8126E–AVR–07/10 : Input Threshold Voltage vs RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC 2.5 2 1.5 1 0.5 0 1 Input Hysteresis vs ...

Page 150

... BOD, Bandgap and Reset Figure 19-51. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.4 4.35 4.3 4.25 4.2 Figure 19-52. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) ATtiny13A 150 BOD THRESHOLDS vs. TEMPERATURE -60 -40 -20 0 Temperature (C) BOD THRESHOLDS vs. TEMPERATURE 2.8 2.75 2.7 2.65 2.6 -60 -40 ...

Page 151

Figure 19-53. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) Figure 19-54. Bandgap Voltage vs. V 1.14 1.12 1.08 1.06 8126E–AVR–07/10 BOD THRESHOLDS vs. TEMPERATURE 1.9 1.85 1.8 1.75 1.7 -60 -40 - BANDGAP VOLTAGE vs. V 1.1 1.5 ...

Page 152

... Figure 19-55. V Figure 19-56. V ATtiny13A 152 : Reset Input Threshold Voltage vs RESET INPUT THRESHOLD VOLTAGE vs. VCC V 2.5 2 1.5 1 0.5 0 1 Reset Input Threshold Voltage vs RESET INPUT THRESHOLD VOLTAGE vs. VCC 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 (Reset Pin Read as '1 I/O PIN READ AS ' ...

Page 153

Figure 19-57. V Figure 19-58. Minimum Reset Pulse Width vs. V 8126E–AVR–07/ Reset Input Pin Hysteresis vs RESET PIN INPUT HYSTERESIS vs 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 ...

Page 154

... Internal Oscillator Speed Figure 19-59. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature Figure 19-60. Calibrated 9.6 MHz RC Oscillator Frequency vs. V ATtiny13A 154 CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10 9.9 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1 9 -40 - Temperature (C) CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 10 9 ...

Page 155

Figure 19-61. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value Figure 19-62. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature 8126E–AVR–07/10 CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...

Page 156

... Figure 19-63. Calibrated 4.8 MHz RC Oscillator Frequency vs. V Figure 19-64. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value ATtiny13A 156 CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 5.2 5 4.8 4.6 4.4 4.2 1.5 2 2.5 3 CALIBRATED 4.8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 3 (V) CC ...

Page 157

Figure 19-65. 128 kHz Watchdog Oscillator Frequency vs. V 116000 114000 112000 110000 108000 106000 104000 102000 100000 Figure 19-66. 128 kHz Watchdog Oscillator Frequency vs. Temperature 115000 114000 113000 112000 111000 110000 109000 108000 107000 106000 105000 8126E–AVR–07/10 WATCHDOG ...

Page 158

... ACSR ACD 0x07 ADMUX – 0x06 ADCSRA ADEN 0x05 ADCH 0x04 ADCL 0x03 ADCSRB – 0x02 Reserved 0x01 Reserved 0x00 Reserved ATtiny13A 158 Bit 6 Bit 5 Bit 4 Bit – – – – SP[7:0] – – – – INT0 PCIE – – ...

Page 159

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...

Page 160

... SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ATtiny13A 160 Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word ...

Page 161

Mnemonics Operands ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV Rd, Rr ...

Page 162

... Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 10M1 10-pad Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) ATtiny13A 162 (1) Ordering Code Package ATtiny13A-PU 8P3 ATtiny13A-SU 8S2 ATtiny13A-SH 8S2 ATtiny13A-SHR 8S2 ATtiny13A-SSU 8S1 ATtiny13A-SSH 8S1 ATtiny13A-SSHR ...

Page 163

Packaging Information 23.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

Page 164

... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com ATtiny13A 164 TOP VIEW ...

Page 165

Top View e D Side View End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2325 Orchard Parkway San Jose, CA 95131 ...

Page 166

... TOP VIEW D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny13A 166 TITLE 20M1, 20-pad 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) SIDE VIEW ...

Page 167

Pin TOP VIEW E1 L BOTTOM VIEW Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5. 2. The terminal # Lasser-marked Feature. 2325 Orchard Parkway San Jose, CA 95131 R ...

Page 168

... Errata The revision letters in this section refer to the revision of the ATtiny13A device. 24.1 ATtiny13A Rev. G – H • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the EEPROM at V Problem Fix/Workaround Do not write the EEPROM when V 24.2 ATtiny13A Rev. E – ...

Page 169

Datasheet Revision History Please note that page numbers in this section refer to the current version of this document and may not apply to previous versions. 25.1 Rev. 8126E – 07/10 1. Updated description in 2. Adjusted notes in ...

Page 170

... Added description of new function, “Software BOD Disable”: – Added functional description on – Updated section on – Added register description on – Updated Register Summary on 8. Added description of enhanced function, “Enhanced Power-On Reset”: – Updated ATtiny13A 170 page 31 page 34 “Supply Current of I/O Modules” on page 124 page 158 page 31 ...

Page 171

Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 3 About ......................................................................................................... 6 4 CPU Core .................................................................................................. 7 5 Memories ................................................................................................ 15 6 System Clock and Clock Options ......................................................... 23 7 Power Management and ...

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... System Control and Reset .................................................................... 35 9 Interrupts ................................................................................................ 45 10 I/O Ports .................................................................................................. 49 11 8-bit Timer/Counter0 with PWM ............................................................ 59 12 Timer/Counter Prescaler ....................................................................... 77 13 Analog Comparator ............................................................................... 79 ATtiny13A ii 7.4 Minimizing Power Consumption ......................................................................32 7.5 Register Description ........................................................................................33 8.1 Resetting the AVR ...........................................................................................35 8.2 Reset Sources .................................................................................................36 8.3 Internal Voltage Reference ..............................................................................38 8.4 Watchdog Timer ..............................................................................................38 8 ...

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Analog to Digital Converter .................................................................. 82 15 debugWIRE On-chip Debug System .................................................... 96 16 Self-Programming the Flash ................................................................. 98 17 Memory Programming ......................................................................... 103 8126E–AVR–07/10 13.2 Register Description ........................................................................................80 14.1 Features ..........................................................................................................82 14.2 Overview ..........................................................................................................82 14.3 Operation .........................................................................................................83 14.4 ...

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... Electrical Characteristics .................................................................... 117 19 Typical Characteristics ........................................................................ 124 20 Register Summary ............................................................................... 158 21 Instruction Set Summary .................................................................... 160 22 Ordering Information ........................................................................... 162 23 Packaging Information ........................................................................ 163 ATtiny13A iv 17.4 Signature Bytes .............................................................................................105 17.5 Page Size ......................................................................................................105 17.6 Serial Programming .......................................................................................106 17.7 High-Voltage Serial Programming .................................................................109 17.8 Considerations for Efficient Programming .....................................................113 18 ...

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... ATtiny13A Rev. G – H ...................................................................................168 24.2 ATtiny13A Rev. E – F ....................................................................................168 24.3 ATtiny13 Rev. A – D ......................................................................................168 25.1 Rev. 8126E – 07/10 .......................................................................................169 25.2 Rev. 8126D – 11/09 .......................................................................................169 25.3 Rev. 8126C – 09/09 .......................................................................................169 25.4 Rev. 8126B – ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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