ATTINY13A-SU Atmel, ATTINY13A-SU Datasheet - Page 55

• Manufacturer Part Number: ATTINY13A-SU
• Description: IC MCU AVR 1K FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13A-SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI
• Total Internal Ram Size: 64Byte
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• On-chip Adc: 4-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
• Minimum Operating Temperature: - 40 C
• Package: 8SOIC EIAJ
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Compliant

10.3.1
8126E–AVR–07/10
Alternate Functions of Port B
The overriding signals may not be present in all port pins, but
description applicable to all port pins in the AVR microcontroller family.
Table 10-2 on page 55
indexes from
signals are generated internally in the modules having the alternate function.
Table 10-2.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
The Port B pins with alternate function are shown in
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 10-5 on page 54
Generic Description of Overriding Signals for Alternate Functions
Full Name
Pull-up
Override Enable
Pull-up
Override Value
Data Direction
Override Enable
Data Direction
Override Value
Port Value
Override Enable
Port Value
Override Value
Port Toggle
Override Enable
Digital Input Enable
Override Enable
Digital Input Enable
Override Value
Digital Input
Analog Input/Output
summarizes the function of the overriding signals. The pin and port
are not shown in the succeeding tables. The overriding
Description
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is enabled
when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV
is set/cleared, regardless of the setting of the DDxn,
PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by
the DDOV signal. If this signal is cleared, the Output driver
is enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared,
and the Output Driver is enabled, the port Value is
controlled by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of
the setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
mode).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
This is the Digital Input to alternate functions. In the figure,
the signal is connected to the output of the schmitt-trigger
but before the synchronizer. Unless the Digital Input is used
as a clock source, the module with the alternate function
will use its own synchronizer.
This is the Analog Input/Output to/from alternate functions.
The signal is connected directly to the pad, and can be
used bi-directionally.
Table 10-3 on page
Figure 10-5
56.
serves as a generic
55