ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet
ATTINY15
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ATTINY15 Summary of contents
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... Operating Voltages – 2.7V - 5.5V • Internal 1.6 MHz System Clock Pin Configuration PDIP/SOIC (RESET/ADC0) PB5 (ADC3) PB4 (ADC2) PB3 GND ® 8-bit Microcontroller 1 8 VCC 2 7 PB2 (ADC1/SCK/T0/INT0 PB1 (AIN1/MISO/OC1A PB0 (AIN0/AREF/MOSI) 8-bit Microcontroller with 1K Byte Flash ATtiny15L Rev. 1187D–12/01 1 ...
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... Power-saving modes. The device is manufactured using Atmel’s high-density, nonvolatile memory technology. By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a pow- erful microcontroller that provides a highly flexible and cost-efficient solution to many embedded control applications. The peripheral features make the ATtiny15L particularly suited for battery chargers, lighting ballasts and all kinds of intelligent sensor applications ...
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... Block Diagram 1187D–12/01 Figure 1. The ATtiny15L Block Diagram VCC GND PROGRAM STACK COUNTER POINTER PROGRAM HARDWARE FLASH STACK INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION Z DECODER CONTROL ALU LINES STATUS REGISTER PROGRAMMING ISP MODULE LOGIC DATA REGISTER PORT B PORT B DRIVERS PB0-PB5 ...
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... VCC GND Port B (PB5..PB0) Analog Pins Internal Oscillators ATtiny15L 4 Supply voltage pin. Ground pin. Port 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse and the special function associated with this pin is external Reset ...
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... The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single-register operations are also executed in the ALU. Figure 2 shows the ATtiny15L AVR RISC microcontroller architecture. The AVR uses a Harvard architecture concept with separate memories and buses for program and data memo- ries ...
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... Since all instructions are single 16-bit words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATtiny15L Program Counter is 9 bits wide, thus addressing the 512 words Flash program memory. See page 54 for a detailed description on Flash memory programming. ...
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... The ATtiny15L AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the various addressing modes supported in the ATtiny15L. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. ...
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... I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing using the LPM Instruction ATtiny15L 8 Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 7. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. “n” is the destination or source register address ...
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... A4 followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once more A2 from the hardware stack. The ATtiny15L contains 64 bytes of data EEPROM memory organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 36, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register ...
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... I/O Memory ATtiny15L 10 Figure 11. Single Cycle ALU Operation T1 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back The I/O space definition of the ATtiny15L is shown in Table 2. (1) Table 2. ATtiny15L I/O Space Address Hex Name Function $3F SREG Status Register $3B GIMSK ...
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... Note: 1. Reserved and unused locations are not shown in the table. All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...
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... The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. The ATtiny15L provides eight interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All the inter- rupts are assigned individual enable bits that must be set (one) together with the I-bit in the status register in order to enable the interrupt ...
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... ATtiny15L Reset Sources 1187D–12/01 The ATtiny15L has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POR • External Reset. The MCU is reset when a low-level is present on the RESET pin for more than 500 ns. ...
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... ATtiny15L 14 Table 4. Reset Characteristics (V CC Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold (1) Voltage (falling) RESET Pin Threshold V RST Voltage Brown-out Reset Threshold V BOT Voltage Note: 1. The Power-on Reset will not work unless the supply voltage has been below V (falling) ...
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... Table 5. The RESET signal is activated again, without any delay, when the V Figure 13. “MCU Start-up, RESET Tied POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET ATtiny15L Time-out Number of Cycles 32 µs 8 128 µ 256 ms 64K 8 µ µs ...
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... TOUT Figure 15. External Reset during Operation ATtiny15L has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V the trigger level, the Brown-out Reset is immediately activated. When V above the trigger level, the Brown-out Reset is deactivated after a delay ...
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... Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set (one Watchdog Reset occurs. The bit is reset (zero Power-on Reset writing a logical “0” to the flag. ...
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... ATtiny15L features an internal bandgap reference with a nominal voltage of 1.22V. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator. The 2.56V reference to the ADC is generated from the internal bandgap reference ...
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... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated ...
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... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero ...
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... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “ ...
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... For details, refer to “Sleep Modes” below. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set (one) ...
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... When waking up from the Power-down mode, a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the reset time-out period. ATtiny15L (nominal) at 3.0V and µs 23 ...
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... Peripheral Clock Generation ATtiny15L 24 The internal RC oscillator provides a fixed 1.6 MHz clock (nominal at 5V and 25 ° C). This internal clock is always the system clock of the ATtiny15L. This oscillator can be cali- brated by writing the calibration byte (see page 55) to the OSCCAL register. Bit ...
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... Prescaler 1187D–12/01 The ATtiny15L provides two general purpose 8-bit Timer/Counters. The Timer/Counters hav e se par ate ing s ele cti epar bit ale Timer/Counter0 uses internal clock (CK) as the clock time base. The Timer/Counter1 may use either the internal clock (CK) or the fast peripheral clock (PCK) as the clock time base ...
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... Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 2 – FOC1A: Force Output Compare 1A Writing a logical “1” to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. The Force Out- put Compare bit can be used to change the output pin without waiting for a compare match in timer ...
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... Figure 20. Timer/Counter0 Block Diagram Bit $33 – – – Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. ATtiny15L T/C CLK SOURCE – – CS02 CS01 R R R/W R ...
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... The Timer Counter 0 – TCNT0 ATtiny15L 28 • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer0. Table 9. Clock 0 Prescale Select CS02 CS01 CS00 ...
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... Upon compare match the PWM output is generated. In PWM mode The Timer/Counter counts up to the value specified in output compare register OCR1B and starts again from $00. This feature allows limiting the counter “full” value to a specified ATtiny15L T/C1 OC1A PIN/ PORT PB1 (PWM OUTPUT) TIMER INT ...
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... The Timer/Counter1 Control Register – TCCR1 ATtiny15L 30 value, lower than $FF. Together with the many prescaler options, flexible PWM fre- quency selection is provided. Table 14 lists clock selection and OCR1B values to obtain PWM frequencies from 10 kHz to 150 kHz at 10 kHz steps. Bit ...
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... OCR1B, and starting from $00 up again. When the counter value matches the contents of the Output Compare register OCR1A, the PB1(OC1A) pin is set or cleared according to the settings of the COM1A1/COM1A0 bits in the Timer/Counter1 Control Registers TCCR1. Refer to Table 12 for details. ATtiny15L CS10 Description 0 CK/8 ...
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... ATtiny15L 32 Table 12. Compare Mode Select in PWM Mode COM1A1 COM1A0 Effect on Compare Pin 0 0 Not connected 0 1 Not connected Cleared on compare match (up-counting) (non-inverted PWM). Set 1 0 when TCNT1 = $00. Set on compare match (up-counting) (inverted PWM). Cleared when 1 1 TCNT1 = $00. Note that in PWM mode, writing to the Output Compare OCR1A, the data value is first transferred to a temporary location ...
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... The frequency of the PWM will be Timer Clock Frequency divided by OCR1B value + 1. Table 14. Timer/Counter1 Clock Prescale Select Clock Selection CK PCK/8 PCK/4 PCK/4 PCK/2 PCK/2 PCK/2 PCK/2 PCK/2 PCK PCK PCK PCK PCK PCK ATtiny15L LSB R/W R/W R/W R/W R OCR1B Output PWMn ...
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... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. ...
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... Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 15. Table 15. Watchdog Timer Prescale Select WDP2 WDP1 ATtiny15L WDP0 Time-out Period 0 16K cycles 1 32K cycles 0 64K cycles 1 128K cycles 0 256K cycles 1 512K cycles 0 1024K cycles 1 2048K cycles 35 ...
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... EEDR contains the data read out from the EEPROM at the address given by EEAR. Bit $1C – – – Read/Write Initial value • Bit 7..4 – RES: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 R/W R/W R/W R ...
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... When EERE has been set, the CPU is halted for four cycles before the next instruc- tion is executed. The user should poll the EEWE bit before starting the read operation write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined. ATtiny15L 37 ...
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... Preventing EEPROM Corruption ATtiny15L 38 The calibrated oscillator is used to time EEPROM. In Table 16 the typical programming time is listed for EEPROM access from the CPU. Table 16. Typical EEPROM Programming Times Number of Calibrated RC Parameter Oscillator Cycles EEPROM write 8192 (from CPU) During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly ...
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... ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut- ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical “1” to the flag. ATtiny15L ...
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... Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine the comparator events that trigger the Analog Comparator Inter- rupt ...
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... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATtiny15L features a 10-bit successive approximation ADC. The ADC is connected to a 4-channel Analog Multiplexer that allows one differential voltage input and four sin- gle-ended voltage inputs constructed from the pins of Port B. The differential input (PB3, PB4) is equipped with a programmable gain stage, providing amplification step (20x) on the differential input voltage before the A/D conversion ...
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... Operation ATtiny15L 42 Figure 25. Analog-to-Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER VCC AREF INTERNAL 2.56 V REFERENCE ADC3 ADC2 POS. INPUT MUX ADC1 ADC0 NEG. INPUT MUX The ADC converts an analog input voltage to a 10-bit digital value through successive approximation ...
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... ADC clock frequency. The ADPSn bits in ADCSR are used to generate a proper ADC clock input frequency from any CK frequency above 100 kHz. The prescaler starts counting from the moment ATtiny15L Reset 7-BIT ADC PRESCALER ADC CLOCK SOURCE ...
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... ADCH ADCL MUX and REFS Update ATtiny15L 44 the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the ADC clock cycle ...
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... Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 18. ADC Conversion Time Sample & Hold Condition (Cycles from Start of Conversion) Extended Conversion Normal Conversions ATtiny15L Next Conversion Sign and MSB of Result Conversion Complete Next Conversion 12 13 ...
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... ADC Noise Canceler Function The ADC Multiplexer Selection Register – ADMUX ATtiny15L 46 The ADC features a noise canceler that enables conversion during ADC Noise Reduc- tion mode (see “Sleep Modes” on page 23) to reduce noise induced from the CPU core and other I/O peripherals. If other I/O peripherals must be active during conversion, this mode works equivalently for Idle mode ...
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... Bits 4..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel and Gain Selection Bits 2..0 The value of these bits selects which analog input is connected to the ADC. In case of differential input (PB3 - PB4), gain selection is also made with these bits ...
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... The ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 ATtiny15L 48 • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I- bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond- ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “ ...
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... If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATtiny15L and all analog components in the application should have a separate analog ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB. ...
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... REF V Internal Voltage Reference INT R Reference Input Resistance REF R Analog Input Resistance AIN Note: 1. Values are guidelines only. Actual values are TBD. ATtiny15L 50 Condition Min Single-ended Conversion Differential Conversion Gain = 1x or 20x Single-ended Conversion REF ADC Clock = 200 kHz Single-ended Conversion ...
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... PB5 can sink 12 mA. When pins PB0 to PB4 are used as inputs and are exter- nally pulled low, they will source current (I In ATtiny15L four Port B pins – PB2, PB3, PB4, and PB5 – have alternative functions as inputs for the ADC. If some Port B pins are configured as outputs essential that these do not switch when a conversion is in progress ...
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... Output Note 4,3…0, pin number. On ATtiny15L, PB5 is input or open-drain output. Because this pin is used for 12V pro- gramming, there is no ESD protection diode limiting the voltage on the pin 0.5V. Thus, special care should be taken to ensure that the voltage on this pin ...
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... In Serial Programming mode, this pin serves as the serial data input, MOSI. In normal mode, this pin also serves as the positive input of the On-chip Analog Comparator. In ATtiny15L, this pin can be chosen to be the reference voltage for the ADC. Refer to the section “The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages” for details. ...
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... Note the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny15L is in Power-on Reset. If not, the part can fail to enter programming mode caused by drive contention on PB0 and/or PB5. All Atmel microcontrollers have a three-byte signature code that identifies the device. ...
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... Programming 1187D–12/01 The ATtiny15L has a one-byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address $000 in the signature address space. To make use of this byte, it should be read from this location and written into the normal Flash Program memory ...
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... Power-off sequence: Set PB3 to “0”. Set PB5 to “0”. Turn VCC power off. When writing or reading serial data to the ATtiny15L, data is clocked on the 8 edge of the 16 external clock pulses needed to generate the internal clock. See Figure 31, Figure 32, and Table 26 for an explanation. MSB ...
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... Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L Instruction Instr.1 PB0 0_1000_0000_00 Chip Erase PB1 0_0100_1100_00 PB2 x_xxxx_xxxx_xx PB0 0_0001_0000_00 Write Flash High and Low PB1 0_0100_1100_00 Address PB2 x_xxxx_xxxx_xx PB0 i_i _00 Write Flash PB1 0_0010_1100_00 Low Byte ...
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... Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L Instruction Instr.1 PB0 0_0000_0100_00 Read Lock PB1 0_0100_1100_00 Bits x_xxxx_xxxx_xx PB2 PB0 0_0000_1000_00 Read PB1 Signature 0_0100_1100_00 Bytes x_xxxx_xxxx_xx PB2 PB0 0_0000_1000_00 Read PB1 Calibration 0_0100_1100_00 Byte x_xxxx_xxxx_xx PB2 Note address high bits ...
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... Figure 33. Serial Programming and Verify PB5 (RESET) GND GND ATtiny15L VALID IVSH SHIX SHSL SLSH SHOV = 25 ° C ± 10%, A Min Typ 25.0 25.0 50.0 50.0 10.0 16.0 2.7 - 5.5V ATtiny15/L VCC SCK PB2 MISO PB1 MOSI PB0 Max Units 32 ...
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... High: > 2 MCU clock cycles When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK. When reading data from the ATtiny15L, data is clocked on the falling edge of SCK. See Figure 34, Figure 35, and Table 28 for timing details. To program and verify the ...
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... See Table 30 for WD_PROG_EE t and t values. WD_PROG_FL WD_PROG_EE Figure 34. Low-voltage Serial Programming Waveforms SERIAL DATA INPUT MSB PB0(MOSI) SERIAL DATA OUTPUT MSB PB1(MISO) SERIAL CLOCK INPUT PB2(SCK) ATtiny15L before programming the next WD_PROG_FL LSB LSB 61 ...
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... Lock bit Lock bit CKSEL0 Fuse 4 = CKSEL1 Fuse 5 = RSTDISBL Fuse 6 = SPIEN Fuse 7 = BODEN Fuse 8 = BODLEVEL Fuse ATtiny15L 62 (1) Instruction Format Byte 2 Byte 3 Byte4 0101 0011 xxxx xxxx xxxx xxxx 100x xxxx xxxx xxxx ...
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... MOSI Hold after SCK High SHOX t SCK Low to MISO Valid SLIV Table 29. Minimum Wait Delay after the Chip Erase Instruction Symbol t WD_ERASE Table 30. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM ATtiny15L t t SLSH SHOX t SHSL = -40 ° ° Min Typ = 2.7 - 5.5V) 0.8 1 ...
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... Output Low Voltage V OL PB5 (4) Output High Voltage V OH Port B Input Leakage Current I IL I/O Pin Input Leakage Current I IH I/O Pin R I/O Pin Pull-up I/O I Power Supply Current CC ATtiny15L 64 *NOTICE: + 0.5V CC Condition Min Except (XTAL) -0.5 XTAL -0.5 Except (XTAL, RESET) 0 XTAL 0 RESET 0. mA ...
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... CC -50 2. 4.0V CC may exceed the related specification. OL may exceed the related specification. Pins are not guaranteed to source current OH ATtiny15L Typ Max Units 40.0 50.0 750.0 500 3V) under steady state 5V, 1 3V) under steady state ...
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... Typical Characteristics ATtiny15L 66 The following charts show typical behavior. These data are characterized but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. The current consumption is a function of several factors such as: Operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature ...
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... Common Mode Voltage (V) Note: 1. Analog Comparator offset voltage is measured as absolute offset. Figure 38. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) ATtiny15L ˚ 2.5 3 3 2.7V ...
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... ATtiny15L 68 Figure 39. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 40. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 1,5 2 2,5 3 Note: 1. Sink and source capabilities of I/O ports are measured on one pin at a time. ...
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... ˚ A 100 ˚ 0.5 1 1.5 Figure 42. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ˚ 0.5 1 ATtiny15L 2.5 3 3.5 4 4 2.7V cc 1.5 2 2 ...
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... ATtiny15L 70 Figure 43. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 44. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0 ...
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... I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 46. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 ATtiny15L ˚ ˚ 1 2.7V cc 1.5 2 2 ...
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... ATtiny15L 72 Figure 47. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 48. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0. ˚ A 4.0 5 ˚ A 4.0 5 1187D–12/01 ...
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... ATtiny15L Register Summary Address Name Bit 7 $3F SREG I $3E Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 - $32 TCNT0 $31 OSCCAL $30 TCCR1 CTC1 $2F TCNT1 $2E OCR1A $2D OCR1B $2C SFIOR - $2B Reserved $2A Reserved $29 Reserved $28 Reserved $27 Reserved $26 Reserved $25 Reserved $24 Reserved $23 Reserved $22 Reserved $21 WDTCR - $20 Reserved $1F Reserved ...
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... ATtiny15L Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers SUB Rd, Rr Subtract Two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry Two Registers ...
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... ATtiny15L Instruction Set Summary (Continued) Mnemonic Operands Description BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register CBI P, b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left through Carry ROR Rd Rotate Right through Carry ASR ...
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... Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) ATtiny15L 76 Ordering Code Package ATtiny15L-1PC 8P3 ATtiny15L-1SC 8S2 ATtiny15L-1PI 8P3 ATtiny15L-1SI 8S2 Package Type Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 1187D–12/01 ...
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... REV. A 04/11/2001 1187D–12/01 10.16(0.400) 9.017(0.355) PIN 1 254(0.100) BSC 0.381(0.015)MIN 0.559(0.022) 0.356(0.014) 1.78(0.070) 1.14(0.045) 8.26(0.325) 7.62(0.300) 1.524(0.060) 0.000(0.000) 10.90(0.430) MAX *Controlling dimension: Inches ATtiny15L 7.11(0.280) 6.10(0.240) 4.95(0.195) 2.92(0.115) 77 ...
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... PIN 1 0 REF 8 ATtiny15L 78 .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .050 (1.27) BSC .212 (5.38) .203 (5.16) .013 (.330) .004 (.102) .035 (.889) .020 (.508) .330 (8.38) .300 (7.62) .080 (2.03) .070 (1.78) .010 (.254) .007 (.178) 1187D–12/01 ...
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