ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet - Page 54
ATTINY48-MMU
Manufacturer Part Number
ATTINY48-MMU
Description
MCU AVR 5K FLASH 12MHZ 28-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-MMU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28VQFN EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.2.1
9.2.2
54
ATtiny48/88
Pin Change Interrupt Timing
Low Level Interrupt
means that these interrupts can be used for waking the part also from sleep modes other than
Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge, or a low level. This is
configured as described in
INT0 or INT1 interrupts are enabled and are configured as level triggered, the interrupts will trig-
ger as long as the corresponding pin is held low. Note that recognition of falling or rising edge
interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
clkI/O” on page
An example of timing of a pin change interrupt is shown in
Figure 9-1.
Low level interrupts on INT0 and INT1 are detected asynchronously. This means that the inter-
rupt sources can be used for waking the part also from sleep modes other than Idle (the I/O
clock is halted in all sleep modes except Idle mode).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
pcint_setflag
pcint_in_(0)
PCINT(0)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
Timing of pin change interrupts
28.
LE
pin_lat
D
“EICRA – External Interrupt Control Register A” on page
Q
pin_sync
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
clk
Figure
9-1.
pcint_syn
pcint_setflag
8008G–AVR–04/11
“I/O Clock –
55. When
PCIF
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