ATTINY48-MMU Atmel, ATTINY48-MMU Datasheet - Page 29

• Manufacturer Part Number: ATTINY48-MMU
• Description: MCU AVR 5K FLASH 12MHZ 28-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire, I2S, SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Package: 28VQFN EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.3
6.1.4
6.1.5
6.2
6.2.1
8008G–AVR–04/11
Clock Sources
Flash Clock – clk
Analog to Digital Converter Clock – clk
High-Speed Two-Wire Interface Clock – clk
External Clock
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The TWI clock controls the operation of the Two-Wire Interface module, when operated in high-
speed mode. In practice, this clock is identical to the source clock of the device. See
Generator Unit” on page
The device can use any of the following sources for the system clock:
The clock source is selected using CKSEL fuses. See
Table 6-1.
Notes:
For more information on fuse bits, see
To drive the device from an external clock source, CLKI should be driven as shown in
on page
• External Clock (see
• Calibrated Internal 8MHz Oscillator (see
• Internal 128 kHz Oscillator (see
FLASH
CKSEL[1:0]
10
1. For all fuses “1” means unprogrammed while “0” means programmed.
2. The device is shipped with this option selected.
3. If 8 MHz frequency exceeds the specification of the device (depends on V
30.
00
01
11
(2)
can be programmed in order to divide the internal frequency by 8.
Device Clocking Options
(1)
Device Clocking Option
External Clock
Reserved
Calibrated Internal 8MHz Oscillator
Internal 128 kHz Oscillator
page
135.
ADC
29)
TWIHS
page
“Fuse Bits” on page
31)
page
30)
Table
189.
6-1.
Frequency
0
–
8.0 MHz
128 kHz
–
12 MHz
ATtiny48/88
CC
(3)
), the CKDIV8 fuse
Figure 6-2
“Bit Rate
29